- this project is implementaion of the Swift Act requirment of Speed Control Module
- Ceedling FramWork link.
- after installing ceedling , open terminal in the project home
- ceedling test:all will run all 32 test for all modules [button,motor,main]
- ceedling test:[modulename] will run the test cases for that specific module for example: ceedling test:motor
- ceedling test:motor and ceedling test:all will run the unite test for motor which will mock the input process with the data provided in the last image and append the output to file src/SpeedOut_uniteTesting.txt 10 test cases
- ceedling release will run the relase version, The excutable will be in build/release/SpeedControl.exe running the excutable will take input from input file and append the output to src/SpeedOut_release.txt file
- to test release first place test case record in src/SwitchStateInput.txt with 4 spaces between each entry
- build/release/SpeedControl.exe
- open src/SpeedOut_release.txt this should match the expected value for each test case.
Kindly note that input file has only two test cases just to make sure it is up and running a wider range of tests has been done using unite test over motorSpeedControl task
The project emulate Motor Speed Control system using OS in and output files.
- I chossed to skip the leafe branches of the left side tree as it's already tested as part of the right side
- The test function to test switch coverage are 6 functions one for each branch, The naming convention is:
- test_SpeedControlTask_switchCoverage_TreeBranch_(void)
- This to test the transition between states one transation per test Testing both valid and invalid transitions.
- using gcov tool, The full documented statistics can be found under Documentation/CodeCoverageStatistics.
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ERR_t motor_setAngle(motor_angles_t angle)
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Ranges{ INT_MIN-->MinAngle[10] , MinAngle[10]-->MaxAngle[140] , MaxAngle[140]-->INT_MAX }
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Tested values
- Valid {10,90,140}
- unValid {INT16_MIN,-1,9,141,100,INT16_MAX}
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Buttons_state_t button_getState(Buttons_t btn);
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Ranges{ INT_MIN-->BTN1 , BTN2 , BTN3 , BTN3-->INT_MAX }
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Tested Values
- Valid { BTN1 , BTN2 , BTN3 }
- unValid { INT16_MIN , -1 , NUM_OF_BTNS , INT16_MAX }
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