Create UART Receiver Module

[CCarrMcMahon]

Description:
We need to implement a UART (Universal Asynchronous Receiver/Transmitter) receiver module that includes a FIFO buffer for data storage. This module will receive serial data and convert it to parallel data for further processing. It should also support adjustable data bits and stop bits.

Blocked By: #12

Requirements:

1. Baud Rate: The module should support a configurable baud rate and handle standard UART baud rates such as 9600, 115200, etc.
2. Data Format: The receiver should support adjustable data bits and stop bits (e.g., 7, 8, or 9 data bits; 1 or 2 stop bits).
3. Parity Check: Implement optional parity checking.
4. FIFO Buffer: Utilize the Create FIFO Buffer Module #12 module for buffering received data.
5. Error Handling: The module should detect framing errors, parity errors, and buffer overflows.
6. Interrupts: Provide signals for data-ready and error conditions.
7. Testbench: Develop a comprehensive testbench to validate the functionality of the UART receiver module.

Tasks:

1. Design the core logic for the UART receiver, including support for adjustable data bits and stop bits.
2. Integrate the fifo_buffer module for data storage.
3. Implement error detection and handling mechanisms.
4. Create a testbench to verify the module's functionality.
5. Document the design and functionality.