VLSI Front End Engineer

Topics to cover for Verification

1. Digital systems
2. Verilog
3. System Verilog
4. Static Timing Analysis (STA)
5. UVM

Resources

Books

1. Verilog HDL A guide to Digital Design and Synthesis by Samir Palnitkar
2. Advanced Digital Design With The Verilog HDL By Michael D Ciletti
3. Writing Testbenches: Functional Verification of HDL Models by Janick Bergeron.
4. System Verilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear.
5. Static Timing Analysis for Nanometer Designs: A Practical Approach by J. Bhasker and Rakesh Chadha.
6. IEEE LRM for System Verilog and Verilog.
7. LRM for System Verilog

Web

1. Hardware Modeling using Verilog by Prof. Indranil Sengupta - NPTEL
2. Architectural Design of Digital Integrated Circuits by Indranil Hatai - NPTEL
3. Chipverify for System Verilog, UVM.
4. Verification Guide for System Verilog,
5. Doulos for System Verilog
6. Eda playground for practicing codes
7. Advanced Resources on System Verilog and UVM
8. Books by Stuart Sutherland(https://www.sutherland-hdl.com/)
9. EE 4755, Digital Design Using HDLs

Youtube Channels

1. Anas Salah Eddin https://www.youtube.com/@anassalaheddin1258
2. H. R. LEPROFESSEUR https://www.youtube.com/@Leprofesseur
3. Vipin Kizheppatt https://www.youtube.com/@TheVipinkmenon
4. Mohammad S. Sadri https://www.youtube.com/@MohammadSSadri
5. Michael ee https://www.youtube.com/@Michael_ee

Apart from these, one must learn

1. Linux commands
2. Makefile
3. Bash/shell scripting
4. Perl / Python scripting
5. At least one industry-standard protocol - for example, AMBA (AXI), RISC5, PCIe, etc.
6. TCL