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Edison is a RISCV code IDE for simulating and debugging RISCV code. Its written in typescript and uses react for UI. It is made for educational purposes and is not intended to be used in production. It is not fully compliant with RISC-V specification, but it can run some simple programs. Also emulates pipelined CPU with 4 stages.

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GangOfUlpgc/edison-risc-v-simulator

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Edison

Edison is a RISCV code IDE for simulating and debugging RISCV code. Its written in typescript and uses react for UI. It is made for educational purposes and is not intended to be used in production. It is not fully compliant with RISC-V specification, but it can run some simple programs. Also emulates pipelined CPU with 4 stages: fetch, decode, execute, writeback.

Its powered by Vega engine, which is a RISC-V emulator written in typescript for RCV32I instruction set. You can find more information about Vega engine down below.

Code editor features

  • Syntax highlighting
  • Code completion
  • Code formatting
  • Code folding
  • Code snippets
  • Code linting
  • Code debugging
  • Code breakpoints

Simulation view features

  • General purpose registers view
  • Instruction Memory view
  • Data Memory view
  • Pipeline view
  • Disassembly view
  • Datapath simulation view

Usage

To run the IDE you need to have nodejs installed on your machine. You can install it from here.

To start using edison you can simply clone this repository and install dependencies:

git clone
cd edison
npm install

Then you can start the IDE:

npm run dev

or if you are using yarn:

yarn dev

Vega Engine

Vega engine is a RISC-V emulator written in typescript for RCV32I instruction set. Its made for educational purposes and is not intended to be used in production. It is not fully compliant with RISC-V specification, but it can run some simple programs. Also emulates pipelined CPU with 4 stages: fetch, decode, execute, writeback.

Features

  • RCV32I instruction set
  • 4 stage pipelined CPU
  • 32 registers
  • 4KB memory

Currently supported instructions

We have support only for this instructions. If you want to contribute adding new instructions it will be a great support.

  • srl x0, x0, x1
  • sll x0, x0, x1
  • lw x0, 0(x1)
  • sw x0, 0(x1)
  • ld x0, 0(x1)
  • sd x0, 0(x1)
  • beq x0, x1, x1
  • add x0, x0, x1
  • sub x0, x0, x1
  • and x0, x0, x1
  • or x0, x0, x1
  • xorx0, x0, x1

Usage

To run the emulator you need to have nodejs installed on your machine. You can install it from here. To add vega engine to your project you need to install it from npm:

npm install @riscv/vega

Then you can import it in your project:

import { Vega } from "@riscv/vega";

To run the emulator you need to create an instance of Vega class use the run method passing the path to the binary file as an argument:

const vega = new Vega();
vega.run("path/to/binary/file");

Contributing

If you are interested in contributing to the development of Edison or the Vega engine, your contributions are more than welcome! You can contribute in various ways such as adding new features, improving the UI, writing documentation, fixing bugs, and adding more RISC-V instructions to the Vega engine.

To contribute, please follow these steps:

  1. Fork the repository.
  2. Create a new branch for your feature (git checkout -b feature/amazing-feature).
  3. Commit your changes (git commit -am 'Add some amazing feature').
  4. Push to the branch (git push origin feature/amazing-feature).
  5. Open a new Pull Request.

Before sending a Pull Request, please make sure your code adheres to the coding conventions used throughout the project (indentation, comments, naming conventions, etc.) and that all tests are passing.

Reporting Issues

If you encounter any bugs or issues with Edison or the Vega engine, please report them using the GitHub issues tracker. Be sure to include detailed steps to reproduce the issue, as well as information about your environment (operating system, Node.js version, etc.).

Documentation

You can find more detailed documentation on how to use Edison and the Vega engine within the docs directory of this repository. This includes tutorials on how to write RISC-V programs, how to use the code editor and simulation view features, and how to extend the Vega engine with additional RISC-V instructions.

License

Edison and the Vega engine are open-source projects licensed under the MIT license. This means you are free to use, share, and modify the software as long as you include the original copyright and license notice in any copies or substantial portions of the software.

Acknowledgments

This project would not be possible without the contributions of the RISC-V community and everyone who has contributed to the development of Edison and the Vega engine. Thank you!

Support

If you find this project useful, please consider supporting it by starring the repository on GitHub, contributing to the project, or donating to the developers.

For more information, support, or to discuss Edison and the Vega engine with other users and developers, please join our Discord server or subscribe to our mailing list.

Enjoy coding with Edison and exploring the RISC-V architecture!

About

Edison is a RISCV code IDE for simulating and debugging RISCV code. Its written in typescript and uses react for UI. It is made for educational purposes and is not intended to be used in production. It is not fully compliant with RISC-V specification, but it can run some simple programs. Also emulates pipelined CPU with 4 stages.

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