Merge pull request #146 from JITx-Inc/PROD-361-pin-to-port

Rename make-pin

src/bundles/comms.stanza

@@ -37,8 +37,8 @@ pcb-bundle smbus-b (pins:Collection<SMBUSPins>):
   port smbdat
   for p in pins do :
     switch(p) :
-      SMBALERT#  : make-pin(`smbalert#)
-      SMBSUS#    : make-pin(`smbsus#)
+      SMBALERT#  : make-port(`smbalert#)
+      SMBSUS#    : make-port(`smbsus#)
 
 doc: \<DOC>
 Configurable SMBus Bundle
@@ -128,9 +128,9 @@ pcb-bundle spi-b (pins:Collection<SPIPins>):
   port sck
   for p in pins do :
     switch(p) :
-      SPI-CS  : make-pin(`cs)
-      SPI-COPI : make-pin(`copi)
-      SPI-CIPO : make-pin(`cipo)
+      SPI-CS  : make-port(`cs)
+      SPI-COPI : make-port(`copi)
+      SPI-CIPO : make-port(`cipo)
 
 doc: \<DOC>
 SPI Bundle Generator
@@ -204,7 +204,7 @@ public pcb-bundle wide-spi (width:Int, pins:Collection<SPIPins>):
   port data : pin[width]
   for p in pins do :
     switch(p):
-      SPI-CS : make-pin(`cs)
+      SPI-CS : make-port(`cs)
       else:
         throw $ ValueError("Wide-SPI does not support pin type: %_" % [p])
 
@@ -270,16 +270,16 @@ pcb-bundle uart-b (pins:Collection<UARTPins>):
   name = "UART"
   for p in pins do :
     switch(p) :
-      UART-DTR : make-pin(`dtr)
-      UART-CTS : make-pin(`cts)
-      UART-DCD : make-pin(`dcd)
-      UART-RI  : make-pin(`ri)
-      UART-DSR : make-pin(`dsr)
-      UART-RTS : make-pin(`rts)
-      UART-CK : make-pin(`ck)
-      UART-DE : make-pin(`de)
-      UART-RX : make-pin(`rx)
-      UART-TX : make-pin(`tx)
+      UART-DTR : make-port(`dtr)
+      UART-CTS : make-port(`cts)
+      UART-DCD : make-port(`dcd)
+      UART-RI  : make-port(`ri)
+      UART-DSR : make-port(`dst)
+      UART-RTS : make-port(`rts)
+      UART-CK : make-port(`ck)
+      UART-DE : make-port(`de)
+      UART-RX : make-port(`rx)
+      UART-TX : make-port(`tx)
 
 doc: \<DOC>
 UART Bundle Generator

src/bundles/debug.stanza

@@ -34,7 +34,7 @@ pcb-bundle swd-b (pins:Collection<SWDPins>):
   port swdclk
   for p in pins do:
     switch(p):
-      SWD-SWO: make-pin(`swo)
+      SWD-SWO: make-port(`swo)
 
 doc: \<DOC>
 Serial Wire Debug Bundle Generator
@@ -44,4 +44,4 @@ Serial Wire Debug Bundle Generator
 @member swo Optional Trace Data Line
 <DOC>
 public defn swd (pins:SWDPins ...):
-  swd-b(pins)
+  swd-b(pins)

src/protocols/ethernet/utils.stanza

@@ -16,6 +16,6 @@ public defn inject-optional-mii-pins (pins:Collection<MIIPins>) :
   inside pcb-bundle:
     for p in pins do :
       switch(p) :
-        MII-COL: make-pin(`col)
-        MII-CS: make-pin(`cs)
-        MII-TXER: make-pin(`tx-er)
+        MII-COL: make-port(`col)
+        MII-CS: make-port(`cs)
+        MII-TXER: make-port(`tx-er)

src/protocols/pcie.stanza

@@ -120,7 +120,7 @@ pcb-bundle pcie-control-b (pins:Collection<PCIePins>) :
   port CLKREQ#         ; clock request
   for p in pins do :
     switch(p) :
-      PCIe-PRSNT# : make-pin(`PRSNT#) ; hot plug detection
+      PCIe-PRSNT# : make-port(`PRSNT#) ; hot plug detection
 
 doc: \<DOC>
 @brief PCI-e Control bundle