Merge branch 'main' into al/lpddr4

examples/landpatterns/SMT.stanza

@@ -25,28 +25,67 @@ pcb-symbol test-sym:
     number-size = 0.762
     name-size = 0.762
 
-pcb-component test-SMT:
+pcb-symbol test-sym-pol:
+  pin a at Point(-2.54, 2.54) with :
+    direction = Left
+    length = 2.54
+    number-size = 0.762
+    name-size = 0.762
+
+  pin c at Point(-2.54, 0.0) with :
+    direction = Left
+    length = 2.54
+    number-size = 0.762
+    name-size = 0.762
+
+pcb-component test-SMT (case:String):
 
   pin-properties :
     [pin:Ref | pads:Ref ... | side:Dir | bank:Int]
     [p[1] | p[1] | Up |  0]
     [p[2] | p[2] | Down | 0]
 
   assign-symbol(test-sym)
-  val chip-def = chips["1206"]
-  val pkg = SMT-Chip(
+  val pkg = get-resistor-pkg(case, DensityLevelC)
+
+  val lp = create-landpattern(pkg)
+  assign-landpattern(lp)
+
+pcb-component test-SMT-pol (case:String):
+  pin-properties :
+    [pin:Ref | pads:Ref ... | side:Dir | bank:Int]
+    [a | a | Up |  0]
+    [c | c | Down | 0]
+
+  assign-symbol(test-sym-pol)
+
+  val chip-def = get-chip-def(case)
+  val pkg = SMT-Capacitor(
     chip-def,
+    polarized? = true
     density-level = DensityLevelC
   )
-
-  ; val pkg = get-chip-pkg("1210", DensityLevelB)
-
   val lp = create-landpattern(pkg)
   assign-landpattern(lp)
 
+
 pcb-module test-design:
-  inst c : test-SMT
-  place(c) at loc(0.0, 0.0) on Top
+  inst C1 : test-SMT("1206")
+  place(C1) at loc(0.0, 0.0) on Top
+
+  inst C2 : test-SMT-pol("1206")
+  place(C2) at loc(2.5, 0.0) on Top
+
+  inst C3 : test-SMT("0402")
+  ; place(C3) at loc(0.0, 0.0) on Top
+  inst C4 : test-SMT-pol("0402")
+
+  inst C5 : test-SMT("0603")
+  inst C6 : test-SMT-pol("0603")
+
+  inst C7 : test-SMT("0805")
+  inst C8 : test-SMT-pol("0805")
+
 
 
 ; Set the top level module (the module to be compile into a schematic and PCB)

examples/protocols/displayport/displayport-src.stanza

@@ -81,7 +81,7 @@ public pcb-component component :
 
   val box-params = BoxSymbolParams(
     show-grid = false
-    col-width = 1
+    min-col-width = 1
   )
 
   val box = BoxSymbol(self, params = box-params)

examples/protocols/pcie/pcie-src.stanza

@@ -97,7 +97,7 @@ public pcb-component component :
 
   val box-params = BoxSymbolParams(
     show-grid = false
-    col-width = 1
+    min-col-width = 1
   )
 
   val box = BoxSymbol(self, params = box-params)

examples/symbols/box-symbol.stanza

@@ -297,8 +297,8 @@ pcb-component test-default-align:
 
   val box = BoxSymbol(self, params = BoxSymbolParams(
     show-grid = true
-    col-width = 10
-    row-width = 5))
+    min-col-width = 10
+    min-row-width = 5))
   set-grid(box, [2,2])
   set-alignment(N, self.rail.V+)
   set-alignment(S, self.rail.V-)
@@ -332,8 +332,8 @@ pcb-component test-pad-ref:
     [ADDR[1] | p[4] | Right | 1 | "A1" ]
 
   val box = BoxSymbol(self, params = BoxSymbolParams(
-    col-width = 10
-    row-width = 5
+    min-col-width = 10
+    min-row-width = 5
     pad-ref-size = 2.0))
   set-grid(box, [2,2])
   set-alignment(N, self.rail.V+)
@@ -407,8 +407,8 @@ pcb-component test-pin-pitch:
 
   val box = BoxSymbol(self, params = BoxSymbolParams(
     show-grid = true
-    col-width = 10
-    row-width = 5
+    min-col-width = 10
+    min-row-width = 5
     pin-pitch = 5.0))
   set-grid(box, [2,2])
   set-alignment(N, self.rail.V+)
@@ -444,8 +444,8 @@ pcb-component test-up-column:
 
   val box = BoxSymbol(self, params = BoxSymbolParams(
     show-grid = true
-    col-width = 1
-    row-width = 5
+    min-col-width = 1
+    min-row-width = 5
   ))
   set-grid(box, [3,3], Ref("test"))
   set-alignment(N, self.rail.V+)
@@ -485,7 +485,7 @@ pcb-component test-even-row:
     ;col-width = 1
     ; line-width = 0.4
     ; pin-length = 4.4
-    row-width = 5
+    min-row-width = 5
   ))
   set-grid(box, [2, 1])
   set-alignment(N, self.rail.V+)
@@ -521,7 +521,7 @@ pcb-component test-group-margin:
 
   val box = BoxSymbol(self, params = BoxSymbolParams(
     show-grid = true
-    row-width = 5
+    min-row-width = 5
   ))
   set-grid(box, [2, 2])
 

slm.toml

@@ -1,4 +1,4 @@
 name = "jsl"
-version = "0.5.1"
+version = "0.6.2"
 [dependencies]
-maybe-utils = { git = "StanzaOrg/maybe-utils", version = "0.1.6"}
+maybe-utils = { git = "StanzaOrg/maybe-utils", version = "0.1.6"}

src/design/introspection.stanza

@@ -480,6 +480,58 @@ public defn get-connected-net (pt:JITXObject, cxt:JITXObject = self) -> Maybe<JI
       else:
         None()
 
+doc: \<DOC>
+Get all net statements associated with a module or component port
+
+This function must be called from within a `pcb-module` context.
+
+Note that this function will fail to find a net if the passed `pt`
+port is not part of a component or module in the local context.
+For example, if the design contains:
+
+```stanza
+pcb-module wrapper:
+  port GND
+  inst C : some-component
+
+  ; `INT` is defined only in the `wrapper`
+  ;   context.
+  net INT (C.internal-port, ...)
+
+pcb-module top-level:
+
+  port pwr : power
+  inst W : wrapper
+  net GND (W.GND)
+  net (GND, pwr.V-)
+
+  ; This will return two nets: one for each statement above
+  val n1 = get-connected-nets(W.GND)
+
+  ; This will return an empty tuple 
+  val n2 = get-connected-nets(W.C.internal-port)
+```
+
+`n1` will be a tuple of two `net` objects, since
+there are two `net` statements defined in the `pcb-module` context.
+
+The `n2` invocation will fail to find `INT` as the net
+for `W.C.internal-port` and return an empty tuple 
+
+@param pt Port of a component or module in this module context.
+@param cxt Optional context to search. The default value is `self`.
+@return If a connection is found - this function returns the Net as
+a JITXObject. If no connection is found - then None().
+<DOC>
+public defn get-connected-nets (pt:JITXObject, cxt:JITXObject = self) -> Tuple<JITXObject>:
+  inside pcb-module:
+    to-tuple $
+      for n in nets(cxt) seq? :
+        if connected?([pt, n]):
+          One(n)
+        else:
+          None()
+
 doc: \<DOC>
 Get the net associated with a module or component port
 
@@ -520,9 +572,15 @@ public pcb-struct jsl/design/introspection/PortInfo :
   ; Ideally - this is a `Maybe` but that isn't supported
   ;   yet.
   ; TODO - consider shifting to `Maybe` in the future.
-  connected-net:JITXObject|False
+  connected-nets:Tuple<JITXObject>
   pad-set:Tuple<jsl/landpatterns/introspection/PadInfo>
 
+; Support `connected-net`, as the field changed from an optional
+; value to a Tuple
+public defn connected-net (p:PortInfo) -> JITXObject|False :
+  if empty?(connected-nets(p)) : false
+  else : connected-nets(p)[0]
+
 doc: \<DOC>
 Extract Port Info from a port `JITXObject`
 @param pt Port referenced from an component object, typically
@@ -538,7 +596,5 @@ public defn get-port-info (pt:JITXObject) -> PortInfo:
         val lp-pds = value(given)
         to-tuple $ for lp-pd in lp-pds seq:
           get-pad-info(lp-pd)
-    val con-net = match(get-connected-net(pt)):
-      (_:None): false
-      (given:One<JITXObject>): value(given)
-    PortInfo(con-net, pd-info)
+    val con-nets = get-connected-nets(pt)
+    PortInfo(con-nets, pd-info)

src/landpatterns/BGA/package.stanza

@@ -198,7 +198,8 @@ public defn compute-overall-outline (
 
   val pkg-outline = bounds $ envelope(body, density-level = density-level)
   val lp-pads = get-pads(vp)
-  val pad-outline = bounds(lp-pads, layer-spec = SolderMask(Top))
+  val pad-outline* = bounds(lp-pads, layer-spec = SolderMask(Top))
+  val pad-outline = fatten(mask-clearance + (line-width / 2.0), pad-outline*)
   val overall = union(pkg-outline, pad-outline)
   LineRectangle(overall, line-width = line-width)
 

src/landpatterns/QFP.stanza

@@ -202,62 +202,15 @@ public defmethod courtyard-excess (pkg:QFP) -> Double :
   val fillets = lead-fillets(protrusion, density-level = density-level(pkg))
   courtyard-excess(fillets)
 
-; Compute the Box bounding the _interior_ of the pads
-; Only works on rectangular landpatterns
-; Is there a less ugly way to do this?
-defn pad-interior-bounds (vp:VirtualLP, side:Side) :
-  val xset = HashSet<Double>()
-  val yset = HashSet<Double>()
-  ; Collect all x- and y-coordinates from pads
-  for p in get-pads(vp) :
-    val bx = bounds([p], layer-spec = SolderMask(side))
-    add(xset, x(lo(bx)))
-    add(xset, x(hi(bx)))
-    add(yset, y(lo(bx)))
-    add(yset, y(hi(bx)))
-  val xs = qsort $ to-tuple(xset)
-  val ys = qsort $ to-tuple(yset)
-  val lo = Point(xs[1], ys[1])
-  val hi = Point(xs[length(xs) - 2], ys[length(ys) - 2])
-  Box(lo, hi)
-
-public defn QFP-pkg-outline (
-  pkg:QFP,
-  vp:VirtualLP
-  --
-  line-width:Double,
-  mask-clearance:Double,
-  side:Side = Top
-  ):
-  val pkg-body = package-body(pkg)
-  ; Package bounding box
-  val pkg-outline = bounds $ envelope(pkg-body, density-level = density-level(pkg))
-  ; Interior outline of pads; shrunk by soldermask-clearance
-  val pad-interior = shrink(mask-clearance + line-width / 2.0, pad-interior-bounds(vp, side))
-  ; Select smaller box
-  val pkg-outline* =
-    if area(pkg-outline) < area(pad-interior) : pkg-outline
-    else : pad-interior
-  LineRectangle(pkg-outline*, line-width = line-width)
-
-public defn QFP-outline (
-  pkg:QFP,
-  vp:VirtualLP
-  --
-  line-width:Double = default-silk-width(),
-  mask-clearance:Double = default-mask-clearance(),
-  side:Side = Top
-  ):
-  val outline-geom =
-    QFP-pkg-outline(pkg, vp, line-width = line-width, mask-clearance = mask-clearance, side = side)
-
-  add-artwork(vp, Silkscreen("outline", side), outline-geom, class = "outline")
-
 public defmethod build-silkscreen (
   pkg:QFP,
   vp:VirtualLP
   ) -> False:
-  QFP-outline(pkg, vp)
+
+  val outline = InterstitialOutline(
+    pkg-body = package-body(pkg)
+  )
+  build-outline(outline, vp)
 
   build-smd-pin-1-dot(
       vp,

src/landpatterns/SOIC.stanza

@@ -282,9 +282,10 @@ public defmethod build-silkscreen (
   pkg:SOIC,
   vp:VirtualLP,
   ) -> False :
-  create-silkscreen-pkg-extrema-outline(
-    vp, package-body(pkg),
+  val eo = EdgesOutline(
+    pkg-body = package-body(pkg),
     density-level = density-level(pkg)
   )
+  build-outline(eo, vp)
   build-smd-pin-1-dot(vp, dir = Left)
   add-reference-designator(vp)

src/landpatterns/SON.stanza

@@ -188,10 +188,11 @@ public defmethod build-silkscreen (
   pkg:SON,
   vp:VirtualLP
   ) -> False:
-  create-silkscreen-pkg-extrema-outline(
-    vp, package-body(pkg),
+  val eo = EdgesOutline(
+    pkg-body = package-body(pkg),
     density-level = density-level(pkg)
   )
+  build-outline(eo, vp)
   build-smd-pin-1-dot(
     vp,
     dir = Left,

src/landpatterns/SOP.stanza

@@ -173,10 +173,11 @@ public defmethod build-silkscreen (
   pkg:SOP,
   vp:VirtualLP
   ) -> False:
-  create-silkscreen-pkg-extrema-outline(
-    vp, package-body(pkg),
+  val eo = EdgesOutline(
+    pkg-body = package-body(pkg),
     density-level = density-level(pkg)
   )
+  build-outline(eo, vp)
   build-smd-pin-1-dot(
     vp,
     dir = Left,

src/landpatterns/SOT.stanza

@@ -207,10 +207,11 @@ public defmethod build-silkscreen (
   pkg:SOT,
   vp:VirtualLP
   ) -> False:
-  create-silkscreen-pkg-extrema-outline(
-    vp, package-body(pkg),
+  val eo = EdgesOutline(
+    pkg-body = package-body(pkg),
     density-level = density-level(pkg)
   )
+  build-outline(eo, vp)
   build-smd-pin-1-dot(
     vp,
     dir = Left,