This repository contains the design, simulation, and analysis of a CMOS Inverter using industry-standard tools like Cadence Virtuoso. The project focuses on understanding and optimizing the fundamental building block of digital circuits—the CMOS inverter.
- Key Features: Schematic Design: Implementation of the CMOS inverter with PMOS and NMOS transistors.
- Simulation Analysis: Transient and DC analysis. Propagation delay, rise/fall time, and noise margin calculation. Performance Metrics: Power dissipation, speed, and robustness under various load conditions. Waveform Outputs: Simulated waveforms illustrating the inverter's response to input variations.
- Tools Used: Cadence Virtuoso for schematic design and simulation. Calculator tool for extracting key performance parameters.
- Applications: Serves as the foundation for larger digital systems such as logic gates, flip-flops, and memory circuits.