Added more register options

Protocentral · Mar 22, 2023 · a06ed85 · a06ed85
1 parent ba884ea
commit a06ed85
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Showing 2 changed files with 152 additions and 9 deletions.
diff --git a/src/protocentral_max30001.cpp b/src/protocentral_max30001.cpp
@@ -5,9 +5,14 @@
 // | |  | | | (_) | || (_) | \__/\  __/ | | | |_| | | (_| | |
 // \_|  |_|  \___/ \__\___/ \____/\___|_| |_|\__|_|  \__,_|_|
 
-//////////////////////////////////////////////////////////////////////////////////////////
-//
-//  Demo code for the MAX30001 breakout board
+/* 
+
+*** Example code for MAX30001 ECG breakout board ***
+
+This example assumes that the MAX30001 is used for monitoring ECG and Respiation signals. The BioZ channel 
+is used for respiration measurement and connected accordingly on the breakout board. 
+
+*/
 //
 //  Arduino connections:
 //
@@ -35,6 +40,7 @@
 //
 /////////////////////////////////////////////////////////////////////////////////////////
 
+
 #include <SPI.h>
 #include "protocentral_max30001.h"
 
@@ -175,25 +181,53 @@ void MAX30001::BeginECGOnly()
 
 void MAX30001::BeginECGBioZ()
 {
-     max30001_cnfg_bmux_t cnfg_bmux;
-     max30001_cnfg_bioz_t cnfg_bioz;
+    max30001_cnfg_gen_t cnfg_gen;
+    max30001_cnfg_emux_t cnfg_emux;
+    max30001_cnfg_ecg_t cnfg_ecg;
+    max30001_cnfg_bmux_t cnfg_bmux;
+    max30001_cnfg_bioz_t cnfg_bioz;
 
     _max30001SwReset();
     delay(100);
 
-    _max30001RegWrite(CNFG_GEN, 0xC0004); // ECG & BioZ Enabled , FMSTR = 32768
+    cnfg_gen.bit.en_ulp_lon=0;  //ULP Lead-ON Disabled
+    cnfg_gen.bit.fmstr = 0b00;
+    cnfg_gen.bit.en_ecg = 0b1;
+    cnfg_gen.bit.en_bioz = 0b1;
+
+    cnfg_gen.bit.en_bloff = 0x00; // BioZ digital lead off detection disabled
+    cnfg_gen.bit.en_dcloff=0x00;// DC Lead-Off Detection Disabled
+    cnfg_gen.bit.en_rbias=0b00; // RBias disabled
+    cnfg_gen.bit.rbiasv= 0b01; // RBias =100 Mohm
+    cnfg_gen.bit.rbiasp= 0b00; // RBias Positive Input not connected
+    cnfg_gen.bit.rbiasn= 0b00; // RBias Negative Input not connected
+
+    _max30001RegWrite(CNFG_GEN, cnfg_gen.all);
+    //_max30001RegWrite(CNFG_GEN, 0xC0004); // ECG & BioZ Enabled , FMSTR = 32768
     delay(100);
+
     //_max30001RegWrite(CNFG_CAL, 0x720000); // Calibration sources disabled
 
     _max30001RegWrite(CNFG_CAL, 0x702000); // Calibration sources disabled
     delay(100);
 
+    cnfg_emux.bit.openp = 0;
+    cnfg_emux.bit.openn = 0;
+    cnfg_emux.bit.pol = 0;
+    cnfg_emux.bit.calp_sel = 0;
+    cnfg_emux.bit.caln_sel = 0;
+
     //_max30001RegWrite(CNFG_EMUX, 0x0B0000); // Pins internally connection to ECG Channels
-    _max30001RegWrite(CNFG_EMUX, 0x00); // Pins internally connection to ECG Channels
+    _max30001RegWrite(CNFG_EMUX, cnfg_emux.all); // Pins internally connection to ECG Channels
     delay(100);
 
-    //_max30001RegWrite(CNFG_ECG, 0x825000); // ECG_RATE: 125 SPS,
-    _max30001RegWrite(CNFG_ECG, 0x835000);
+    cnfg_ecg.bit.rate = 0b10;   //Default, 128SPS
+    cnfg_ecg.bit.gain = 0b11;   // 160 V/V
+    cnfg_ecg.bit.dhpf = 0b1;    // 0.5Hz
+    cnfg_ecg.bit.dlpf = 0b01;   // 40Hz
+
+    //_max30001RegWrite(CNFG_ECG, 0x835000);
+    _max30001RegWrite(CNFG_ECG, cnfg_ecg.all);
     delay(100);
 
     cnfg_bmux.bit.openp = 0;

diff --git a/src/protocentral_max30001.h b/src/protocentral_max30001.h
@@ -166,6 +166,34 @@ typedef union max30001_status_reg
 
 } max30001_status_t;
 
+/**
+ * @brief CNFG_GEN (0x10)
+ */
+typedef union max30001_cnfg_gen_reg
+{
+  uint32_t all;
+  struct
+  {
+    uint32_t rbiasn : 1;
+    uint32_t rbiasp : 1;
+    uint32_t rbiasv : 2;
+    uint32_t en_rbias : 2;
+    uint32_t vth : 2;
+    uint32_t imag : 3;
+    uint32_t ipol : 1;
+    uint32_t en_dcloff : 2;
+    uint32_t en_bloff : 2;
+    uint32_t reserved1 : 1;
+    uint32_t en_pace : 1;
+    uint32_t en_bioz : 1;
+    uint32_t en_ecg : 1;
+    uint32_t fmstr : 2;
+    uint32_t en_ulp_lon : 2;
+    uint32_t reserved : 8;
+  } bit;
+
+} max30001_cnfg_gen_t;
+
 /**
  * @brief MNGR_INT (0x04)
  */
@@ -193,6 +221,47 @@ typedef union max30001_mngr_int_reg
 
 } max30001_mngr_int_t;
 
+/**
+ * @brief CNFG_EMUX  (0x14)
+ */
+typedef union max30001_cnfg_emux_reg
+{
+  uint32_t all;
+  struct
+  {
+    uint32_t reserved1 : 16;
+    uint32_t caln_sel : 2;
+    uint32_t calp_sel : 2;
+    uint32_t openn : 1;
+    uint32_t openp : 1;
+    uint32_t reserved2 : 1;
+    uint32_t pol : 1;
+    uint32_t reserved : 8;
+  } bit;
+
+} max30001_cnfg_emux_t;
+
+/**
+ * @brief CNFG_ECG   (0x15)
+ */
+typedef union max30001_cnfg_ecg_reg
+{
+  uint32_t all;
+  struct
+  {
+    uint32_t reserved1 : 12;
+    uint32_t dlpf : 2;
+    uint32_t dhpf : 1;
+    uint32_t reserved2 : 1;
+    uint32_t gain : 2;
+    uint32_t reserved3 : 4;
+    uint32_t rate : 2;
+
+    uint32_t reserved : 8;
+  } bit;
+
+} max30001_cnfg_ecg_t;
+
 /**
  * @brief CNFG_BMUX   (0x17)
  */
@@ -243,6 +312,46 @@ typedef union max30001_bioz_reg
 
 } max30001_cnfg_bioz_t;
 
+/**
+ * @brief CNFG_RTOR1   (0x1D)
+ */
+typedef union max30001_cnfg_rtor1_reg
+{
+  uint32_t all;
+  struct
+  {
+    uint32_t reserved1 : 8;
+    uint32_t ptsf : 4;
+    uint32_t pavg : 2;
+    uint32_t reserved2 : 1;
+    uint32_t en_rtor : 1;
+    uint32_t gain : 4;
+    uint32_t wndw : 4;
+    uint32_t reserved : 8;
+  } bit;
+
+} max30001_cnfg_rtor1_t;
+
+/**
+ * @brief CNFG_RTOR2 (0x1E)
+ */
+typedef union max30001_cnfg_rtor2_reg
+{
+  uint32_t all;
+  struct
+  {
+    uint32_t reserved1 : 8;
+    uint32_t rhsf : 3;
+    uint32_t reserved2 : 1;
+    uint32_t ravg : 2;
+    uint32_t reserved3 : 2;
+    uint32_t hoff : 6;
+    uint32_t reserved4 : 2;
+    uint32_t reserved : 8;
+  } bit;
+
+} max30001_cnfg_rtor2_t;
+
 typedef enum
 {
   SAMPLINGRATE_128 = 128,