revert changes to the timer reset_value setter

RTimothyEdwards · Aug 27, 2023 · 5e426be · 5e426be
1 parent a00c709
commit 5e426be
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Showing 2 changed files with 8 additions and 8 deletions.
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
@@ -168,10 +168,10 @@ always @(posedge clkin or negedge resetn) begin
     if (resetn == 1'b0) begin
 	value_reset <= 32'd0;
     end else begin
-	if (reg_dat_we[3]) value_reset[31:24] <= reg_val_di[31:24];
-	if (reg_dat_we[2]) value_reset[23:16] <= reg_val_di[23:16];
-	if (reg_dat_we[1]) value_reset[15:8] <= reg_val_di[15:8];
-	if (reg_dat_we[0]) value_reset[7:0] <= reg_val_di[7:0];
+	if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24];
+	if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16];
+	if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8];
+	if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0];
     end
 end
 

diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
@@ -171,10 +171,10 @@ always @(posedge clkin or negedge resetn) begin
     if (resetn == 1'b0) begin
 	value_reset <= 32'd0;
     end else begin
-	if (reg_dat_we[3]) value_reset[31:24] <= reg_val_di[31:24];
-	if (reg_dat_we[2]) value_reset[23:16] <= reg_val_di[23:16];
-	if (reg_dat_we[1]) value_reset[15:8] <= reg_val_di[15:8];
-	if (reg_dat_we[0]) value_reset[7:0] <= reg_val_di[7:0];
+	if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24];
+	if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16];
+	if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8];
+	if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0];
     end
 end