caravel_openframe_project physical implementation

openlane/Makefile

@@ -0,0 +1,120 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+export OPENLANE_ROOT=/home/hosni/OpenLane
+export PDK_ROOT=/home/hosni/OpenLane/pdks/
+export PDK=sky130A
+export OPENLANE_TAG=01e67230f35aa4cd08ef33a9f8df8a83f578b710
+
+MAKEFLAGS+=--warn-undefined-variables
+export OPENLANE_RUN_TAG ?= $(shell date '+%y_%m_%d_%H_%M')
+OPENLANE_TAG ?=ed194238ac359aca044c54fa8cbbbd12280e1a8c
+OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
+IT_SCRIPT ?= ./interactive.tcl
+designs = $(shell find * -maxdepth 0 -type d)
+current_design = null
+
+openlane_cmd = \
+	"flow.tcl \
+	-design $$(realpath ./$*) \
+	-save_path $$(realpath ..) \
+	-save \
+	-tag $(OPENLANE_RUN_TAG) \
+	-verbose 1 \
+	-overwrite"
+openlane_cmd_interactive = "flow.tcl -ignore_mismatches -it -file $$(realpath ./$*/$(IT_SCRIPT))"
+openlane_cmd_regression = "cd /openlane && ./run_designs.py \
+													 --regression $$(realpath ./$*/regression.config) \
+													 --threads 6 \
+													 $$(realpath ./$*)"
+
+docker_mounts = \
+	-v $$(realpath $(PWD)/..):$$(realpath $(PWD)/..) \
+	-v $(PDK_ROOT):/pdk \
+	-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+	-v $(PWD):$(PWD) \
+	-v $(HOME):$(HOME)
+
+docker_env = \
+	-e PDK_ROOT=/pdk \
+	-e PDK=$(PDK) \
+	-e MISMATCHES_OK=1 \
+	-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+	-e OPENLANE_RUN_TAG=$(OPENLANE_RUN_TAG) \
+	-w $(PWD)
+
+ifneq ($(OPENLANE_ROOT),)
+$(info openlane $(OPENLANE_ROOT))
+docker_mounts += -v $(OPENLANE_ROOT):/openlane
+docker_mounts += -v $(OPENLANE_ROOT):/openLANE_flow
+endif
+
+ifneq ($(MCW_ROOT),)
+docker_env += -e MCW_ROOT=$(MCW_ROOT)
+docker_mounts += -v $(MCW_ROOT):$(MCW_ROOT)
+endif
+
+docker_startup_mode = $(shell test -t 0 && echo "-it" || echo "--rm" )
+docker_run = \
+	docker run $(docker_startup_mode) \
+	$(docker_mounts) \
+	$(docker_env) \
+	-u $(shell id -u $(USER)):$(shell id -g $(USER))
+
+list:
+	@echo $(designs)
+
+regression-designs=$(designs:%=%-regression)
+.PHONY: $(regression-designs)
+$(regression-designs): %-regression: ./%/regression.config
+	$(docker_run) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_regression)
+
+
+.PHONY: $(designs)
+$(designs) : % : ./%/config.json
+ifneq (,$(wildcard ./$(MAKECMDGOALS)/interactive.tcl)))
+	$(docker_run) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive)
+else
+	# $(MAKECMDGOALS)
+	mkdir -p ./$*/runs/$(OPENLANE_RUN_TAG) 
+	rm -rf ./$*/runs/$*
+	ln -s $$(realpath ./$*/runs/$(OPENLANE_RUN_TAG)) ./$*/runs/$*
+	$(docker_run) \
+		$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd)
+endif
+	@mkdir -p ../signoff/$*/
+	@cp ./$*/runs/$(OPENLANE_RUN_TAG)/OPENLANE_VERSION ../signoff/$*/
+	@cp ./$*/runs/$(OPENLANE_RUN_TAG)/PDK_SOURCES ../signoff/$*/
+	@cp ./$*/runs/$(OPENLANE_RUN_TAG)/reports/*.csv ../signoff/$*/
+
+.PHONY: openlane
+openlane: check-openlane-env
+	if [ -d "$(OPENLANE_ROOT)" ]; then\
+		echo "Deleting exisiting $(OPENLANE_ROOT)" && \
+		rm -rf $(OPENLANE_ROOT) && sleep 2; \
+		fi
+	git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+		cd $(OPENLANE_ROOT) && \
+		export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+		$(MAKE) pull-openlane
+
+.PHONY: check-openlane-env
+check-openlane-env:
+ifeq ($(OPENLANE_ROOT),)
+	@echo "Please export OPENLANE_ROOT"
+	@exit 1
+endif

openlane/openframe_project_wrapper/macro.cfg

@@ -1,3 +1,3 @@
-openframe_example 550 1990 N
+openframe_example 450 1940 N
 vccd1_connection 3122.515 4327.515 N
 vssd1_connection 3122.515 2088.515 N

openlane/openframe_project_wrapper/signoff.sdc

@@ -31,7 +31,7 @@ set_max_fanout 20 [current_design]
 ## FALSE PATHS (ASYNCHRONOUS INPUTS)
 set_false_path -from [get_ports {resetb}]
 set_false_path -from [get_ports {porb}]
-set_false_path -from [get_ports {gpio_in[38]}] -to [get_pins {openframe_example/_34238_/D}]
+set_false_path -from [get_ports {gpio_in[38]}] -to [get_pins {openframe_example/_34243_/D}]
 
 # add loads for output ports (pads)
 set min_cap 0.04

openlane/picosoc/config.json

@@ -83,7 +83,7 @@
     "CLOCK_PORT": "gpio_in[38]",
     "PL_TARGET_DENSITY": 0.28,
     "DIE_AREA_WRAPPER": "0 0 3168.82 4768.82",
-    "DIE_AREA": "0 0 2200 1500",
+    "DIE_AREA": "0 0 2600 1600",
     "RUN_IRDROP_REPORT": 0,
     "BASE_SDC_FILE": "dir::base.sdc",
     "GRT_ALLOW_CONGESTION": 1,
@@ -93,5 +93,5 @@
     "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
     "SYNTH_DEFINES": "PnR",
     "QUIT_ON_HOLD_VIOLATIONS": 0,
-    "GRT_ADJUSTMENT": 0.18
+    "GRT_ADJUSTMENT": 0.19
 }

openlane/picosoc/signoff.sdc

@@ -32,7 +32,7 @@ set_max_fanout 20 [current_design]
 ## FALSE PATHS (ASYNCHRONOUS INPUTS)
 set_false_path -from [get_ports {resetb}]
 set_false_path -from [get_ports {porb}]
-set_false_path -from [get_ports {gpio_in[38]}] -to [get_pins {_34238_/D}]
+set_false_path -from [get_ports {gpio_in[38]}] -to [get_pins {_34243_/D}]
 
 # add loads for output ports (pads)
 set min_cap 0.04

verilog/gl/vccd1_connection.v

@@ -0,0 +1,2 @@
+module vccd1_connection ();
+endmodule

verilog/gl/vssd1_connection.v

@@ -0,0 +1,2 @@
+module vssd1_connection ();
+endmodule

verilog/rtl/openframe_project_wrapper.v

@@ -31,18 +31,8 @@
 
 module openframe_project_wrapper (
 `ifdef USE_POWER_PINS
-    inout vdda,		// User area 0 3.3V supply
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa,		// User area 0 analog ground
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
-    inout vccd,		// Common 1.8V supply
     inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
-    inout vssd,		// Common digital ground
     inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
 `endif
 
     /* Signals exported from the frame area to the user project */

verilog/rtl/picosoc.v

@@ -44,6 +44,7 @@
 /* macro instances in mem_wb.v.	 1024 words = 4kB (2 2kB SRAM modules)	*/
 `define MEM_WORDS 1024
 `ifndef COCOTB_SIM
+`ifndef PnR
 `include "picorv32.v"
 `include "spimemio.v"
 `include "simpleuart.v"
@@ -61,6 +62,7 @@
 `ifdef SIM
 `include "libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `endif
+`endif // PnR
 `endif // COCOTB_SIM
 
 /*--------------------------------------------------------------*/
@@ -145,7 +147,6 @@ module picosoc (
     parameter GPIO_VECTOR_BASE_ADR  = 32'h2500_0000;
     parameter FLASH_CTRL_CFG  = 32'h2D00_0000;
     parameter DEBUG_REGS_CFG  = 32'h4100_0000;
-
     // Wishbone Interconnect 
     localparam ADR_WIDTH = 32;
     localparam DAT_WIDTH = 32;
@@ -249,7 +250,7 @@ module picosoc (
     wire [31:0] cpu_dat_o;
     wire cpu_ack_i;
     wire mem_instr;
-    
+
     picorv32_wb #(
         .STACKADDR(STACKADDR),
         .PROGADDR_RESET(PROGADDR_RESET),
@@ -266,14 +267,14 @@ module picosoc (
         .trap     (trap),
         .irq      (irq),
         .mem_instr(mem_instr),
-        .wbm_adr_o(cpu_adr_o),     
-        .wbm_dat_i(cpu_dat_i),    
-        .wbm_stb_o(cpu_stb_o),    
-        .wbm_ack_i(cpu_ack_i),    
-        .wbm_cyc_o(cpu_cyc_o),    
-        .wbm_dat_o(cpu_dat_o),    
-        .wbm_we_o(cpu_we_o),      
-        .wbm_sel_o(cpu_sel_o)     
+        .wbm_adr_o(cpu_adr_o),
+        .wbm_dat_i(cpu_dat_i),
+        .wbm_stb_o(cpu_stb_o),
+        .wbm_ack_i(cpu_ack_i),
+        .wbm_cyc_o(cpu_cyc_o),
+        .wbm_dat_o(cpu_dat_o),
+        .wbm_we_o(cpu_we_o),
+        .wbm_sel_o(cpu_sel_o)
     );
 
     // Wishbone SPI flash controller
@@ -290,7 +291,7 @@ module picosoc (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
 
-        .wb_adr_i(cpu_adr_o), 
+        .wb_adr_i(cpu_adr_o),
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
@@ -300,7 +301,7 @@ module picosoc (
         .wb_flash_stb_i(spimemio_flash_stb_i),
         .wb_flash_ack_o(spimemio_flash_ack_o),
         .wb_flash_dat_o(spimemio_flash_dat_o),
-        
+
         // Flash Config Register
         .wb_cfg_stb_i(spimemio_cfg_stb_i),
         .wb_cfg_ack_o(spimemio_cfg_ack_o),
@@ -340,7 +341,7 @@ module picosoc (
         .flash_io3_di (cpu_gpio_in[37])
     );
 
-    // Wishbone Slave uart	
+    // Wishbone Slave uart
     wire uart_stb_i;
     wire uart_ack_o;
     wire [31:0] uart_dat_o;
@@ -353,7 +354,7 @@ module picosoc (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
 
-        .wb_adr_i(cpu_adr_o),      
+        .wb_adr_i(cpu_adr_o),
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
@@ -382,7 +383,7 @@ module picosoc (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
 
-        .wb_adr_i(cpu_adr_o),      
+        .wb_adr_i(cpu_adr_o),
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
@@ -418,7 +419,7 @@ module picosoc (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
 
-        .wb_adr_i(cpu_adr_o),      
+        .wb_adr_i(cpu_adr_o),
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
@@ -449,7 +450,7 @@ module picosoc (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
 
-        .wb_adr_i(cpu_adr_o),      
+        .wb_adr_i(cpu_adr_o),
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
@@ -555,7 +556,7 @@ module picosoc (
 	    ) gpio_wb (
 		.wb_clk_i(wb_clk_i),
 		.wb_rst_i(wb_rst_i),
-		.wb_adr_i(cpu_adr_o), 
+		.wb_adr_i(cpu_adr_o),
 		.wb_dat_i(cpu_dat_o),
 		.wb_sel_i(cpu_sel_o),
 		.wb_we_i(cpu_we_o),
@@ -642,7 +643,7 @@ module picosoc (
 
 	assign cpu_gpio_ieb[39] = gpio_loopback_one[39]; /* Flash CSB */
 	assign cpu_gpio_ieb[40] = gpio_loopback_one[40]; /* Flash clock */
-    
+
     endgenerate
 
     /* gpio_vector_wb ---
@@ -664,14 +665,14 @@ module picosoc (
 	.wb_clk_i(wb_clk_i),
 	.wb_rst_i(wb_rst_i),
 
-	.wb_adr_i(cpu_adr_o), 
+	.wb_adr_i(cpu_adr_o),
 	.wb_dat_i(cpu_dat_o),
 	.wb_sel_i(cpu_sel_o),
 	.wb_we_i(cpu_we_o),
 	.wb_cyc_i(cpu_cyc_o),
 
 	.wb_stb_i(gpio_vector_stb_i),
-	.wb_ack_o(gpio_vector_ack_o), 
+	.wb_ack_o(gpio_vector_ack_o),
 	.wb_dat_o(gpio_vector_dat_o),
 
 	/* For an explanation of the mapping of the upper bits of
@@ -710,14 +711,14 @@ module picosoc (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
 
-        .wb_adr_i(cpu_adr_o), 
+        .wb_adr_i(cpu_adr_o),
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
         .wb_cyc_i(cpu_cyc_o),
 
         .wb_stb_i(mem_stb_i),
-        .wb_ack_o(mem_ack_o), 
+        .wb_ack_o(mem_ack_o),
         .wb_dat_o(mem_dat_o)
     );
 
@@ -758,7 +759,7 @@ module picosoc (
 		gpio_vector_stb_i,
 		uart_stb_i,
 		spimemio_flash_stb_i,
-		mem_stb_i }), 
+		mem_stb_i }),
         .wbs_dat_i({
         debug_dat_o,
 		spimemio_cfg_dat_o,
@@ -796,12 +797,12 @@ module picosoc (
 	`ifdef USE_POWER_PINS
 	    .VPWR(VPWR),
 	    .VGND(VGND),
-	`endif		
+	`endif
 	.ext_clk_sel(ext_clk_sel),
 	.ext_clk(cpu_gpio_in[38]),
 	.dll_clk(dll_clk),
 	.dll_clk90(dll_clk90),
-	.resetb(resetb), 
+	.resetb(resetb),
 	.sel(spi_dll_sel),
 	.sel2(spi_dll90_sel),
 	.primdiv(spi_prim_div),