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Verification-of-Sequential-Circuit-using-SAT-Solver

MiniSAT, C++

Developed a C++ code to automate the generation of SAT clauses in CNF form for all logic gates.

Executed unrolling of the sequential circuit to create SAT clauses for comprehensive verification.

Used MiniSAT to identify the input sequence needed to transition from an initial state to a desired state.

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MiniSAT, C++

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