Pull UART Input

cek_prima.vhd

@@ -0,0 +1,47 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+use IEEE.MATH_REAL.ALL;
+use work.all;
+
+entity cek_prima is
+    Port ( clk : in STD_LOGIC;
+           rst : in STD_LOGIC;
+           input_number : in integer range 0 to 131071;
+           is_prime : out STD_LOGIC);
+end cek_prima;
+
+architecture Behavioral of cek_prima is
+    signal n : integer:=2;
+    signal remainder : integer;
+	signal prime : std_logic := '1';
+
+begin
+    process(clk, rst)
+    begin
+        if rst = '1' then
+            n <= 2;
+            prime <= '1';
+        elsif rising_edge(clk) then
+			if n < input_number and prime = '1' then
+				remainder <= (input_number) mod n;
+                    if remainder = 0 then
+                        prime <= '0'; -- Input is not prime
+                    else
+                        prime <= '1'; -- Input is prime
+                    end if;
+	if n = 2 then
+        	n <= n+1;
+	else
+		n <= n+2;
+	end if;
+        end if;
+
+    if input_number = 1 or input_number = 0 then
+		is_prime <= '0';
+	else
+		is_prime <= prime;
+	end if;
+    end process;
+end Behavioral;

comparator_fsm.vhd

@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity comparator_fsm is port (
+	A		: in integer range 0 to 2147483646;
+	m		: in integer range 0 to 131071;
+	comp	: out std_logic_vector(0 downto 0));
+end comparator_fsm;
+
+architecture behavioral of comparator_fsm is
+	begin
+	process(A, m)
+	begin
+	if A >= m then
+		comp <= "1";
+	else
+		comp <= "0";
+	end if;
+	end process;
+end behavioral;

demux.vhd

@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity demux is
+	port( rst, selektor: in std_logic;
+		  input1: in integer range 0 to 65536;
+		  output1: out integer range 0 to 65536;
+		  output2: out integer range 0 to 65536
+	);
+end demux;
+
+architecture demux_arc of demux is
+begin
+	process(rst, selektor, input1)
+	begin
+	if(rst = '1') then
+		output1 <= 0;  
+		output2 <= 0; 
+	elsif selektor = '0' then
+		output1 <= input1; 
+	else
+		output2 <= input1;
+	end if;
+	end process;
+end demux_arc;

fsm.vhd

@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity fsm is
+    port(
+        clk, rst: in std_logic;
+        operation : in std_logic_vector(0 downto 0);
+        comp : in std_logic_vector(0 downto 0);
+        enable, sel : out std_logic
+    );
+end fsm;
+
+architecture Behavioral of fsm is
+    type state is (A, B, C, D);
+    signal current_state, next_state : state;
+
+begin
+    process(rst, clk)
+    begin
+        if rst = '1' then
+            current_state <= A;
+        elsif (clk'event and clk = '1') then
+			current_state <= next_state;
+        end if;
+    end process;
+
+    process(current_state, comp, operation)
+    begin
+        case current_state is
+            when A =>
+				enable <= '0';
+				sel <= '0';
+                if (operation = "1") then 
+                    next_state <= B; 
+                else 
+					next_state <= C;
+                end if;
+
+            when B =>
+				enable <= '0';
+				sel <= '0';         
+				next_state <= D;
+
+            when D =>
+				enable <= '0';
+				sel <= '1';
+                if (comp = "1") then 
+                    next_state <= D; 
+                else 
+					next_state <= C;
+                end if;
+
+            when C =>
+				enable <= '1';
+				sel <= '1';         
+				next_state <= A;
+		end case;
+    end process;
+end Behavioral;

galois_modulo.vhd

@@ -0,0 +1,68 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+use work.all;
+
+entity galois_modulo is port ( 
+	A 		: in integer range 0 to 2147483647;
+    P 		: in integer range 0 to 131072;
+	comp	: in std_logic_vector(0 downto 0);
+    res 	: out integer range 0 to 65536
+    );
+end galois_modulo;
+
+architecture Behavioral of galois_modulo is
+	type states is (s1, s2, s3);
+    signal temp_A					: std_logic_vector(31 downto 0);
+	signal temp_P					: std_logic_vector(31 downto 0);
+	signal temp_result, temp_shift	: std_logic_vector(31 downto 0);
+	signal difference, msb_A, msb_P	: integer;
+begin
+temp_A <= std_logic_vector(to_unsigned(A,32));
+temp_P <= std_logic_vector(to_unsigned(P,32));
+
+--Mencari selisih MSB
+process(temp_A, temp_P)
+begin
+	if comp = "1" then
+		for i in 31 downto 0 loop
+			msb_A <= i;
+			if temp_A(i) = '1' then
+				exit;
+			end if;
+		end loop;
+		for j in 31 downto 0 loop
+			msb_P <= j;
+			if temp_P(j) = '1' then
+				exit;
+			end if;
+		end loop;
+	else
+		msb_A <= 0;
+		msb_P <= 0;
+	end if;
+end process;
+difference <= (msb_A - msb_P);
+
+--Left Shift Modulo and Modulo
+process(temp_A, temp_P, difference, temp_result, temp_shift)
+	variable	k		: integer := 0;
+	variable counter	: integer := 0; 
+begin
+	if comp = "1" then
+		if difference > 0 then
+			for j in 0 to 16 loop
+				exit when j = difference;
+				temp_shift <= temp_P(30 downto 0) & '0';
+			end loop;
+			temp_result <= temp_A xor temp_shift;
+		elsif (difference <= 0) then
+			temp_result <= temp_A xor temp_P;
+		end if;
+	else
+		temp_result <= temp_A;
+	end if;
+end process;
+res <= to_integer(unsigned(temp_result));
+end Behavioral;

galois_multiplus.vhd

@@ -4,39 +4,50 @@ USE ieee.numeric_std.all;
 USE ieee.std_logic_unsigned.all;
 use work.all;
 
-entity galois_multiply is port (
-	A, B	: in integer range 0 to 65536;
-	mode	: in std_logic_vector(0 downto 0);
-	res		: out integer range 0 to 131072);
-end galois_multiply;
+entity galois_multiplus is port (
+	clk					: in std_logic;
+	A, B				: in integer range 0 to 65535;
+	mode				: in std_logic_vector(0 downto 0);
+	res_addition		: out integer range 0 to 65535;
+	res_multiply		: out integer range 0 to 131071
+	);
+end galois_multiplus;
 
-architecture behavioral of galois_multiply is
-	signal num_A	: std_logic_vector(31 downto 0);
+architecture behavioral of galois_multiplus is
 	signal num_B	: std_logic_vector(31 downto 0);
 	signal op		: integer;
-	signal result	: std_logic_vector(31 downto 0);
+	signal result_add	: std_logic_vector(31 downto 0);
+	signal result_mult	: std_logic_vector(31 downto 0);
+	signal num_A_mult	: std_logic_vector(31 downto 0);
+	signal num_A_add	: std_logic_vector(31 downto 0);
 begin
 num_B <= std_logic_vector(to_unsigned(B,32));
 op <= to_integer(unsigned(mode));
-process (num_B, op)
-variable num_1 : std_logic_vector(31 downto 0);
+process (num_B, op, result_add, result_mult, clk)
+variable num_1 	: std_logic_vector(31 downto 0);
 variable temp	: std_logic_vector(31 downto 0):= "00000000000000000000000000000000";
+variable i		: integer:= 0;
 begin
 	num_1 := std_logic_vector(to_unsigned(A,32));
 	if op = 1 then
 		--Operasi Perkalian
-		for i in 0 to 15 loop
+		if rising_edge(clk) then
 			for j in 0 to 15 loop
 				if num_B(j) = '1' then
 					temp(j+i) := temp(j+i) XOR num_1(i);
 				end if;
 			end loop;
-		end loop;
-		result <= temp;
+			i := i + 1;
+		end if;
+		result_mult <= temp;
+		result_add <= "00000000000000000000000000000000";
 	else
-		result <= num_1 XOR num_B;
+		result_mult <= "00000000000000000000000000000000";
+		result_add <= num_1 XOR num_B;
 	end if;
 end process;
-num_A <= result;
-res <= to_integer(unsigned(num_A));
+num_A_mult <= result_mult;
+num_A_add <= result_add;
+res_addition <= to_integer(unsigned(num_A_add));
+res_multiply <= to_integer(unsigned(num_A_mult));
 end behavioral;		

mux.vhd

@@ -0,0 +1,27 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity mux is
+	port( rst: in std_logic;
+		  selektor: in std_logic_vector(0 downto 0);
+		  input1: in integer range 0 to 65536;
+		  input2: in integer range 0 to 65536;
+		  output: out integer range 0 to 65536
+	);
+end mux;
+
+architecture mux_arc of mux is
+begin
+	process(rst, selektor, input1, input2)
+	begin
+	if(rst = '1') then
+		output <= 0; 
+	elsif selektor = "0" then
+		output <= input1; 
+	else
+		output <= input2;
+	end if;
+	end process;
+end mux_arc;

mux3216.vhd

@@ -0,0 +1,26 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity mux3216 is
+	port( rst, selektor: in std_logic;
+		  input1: in integer range 0 to 131071;
+		  input2: in integer range 0 to 65535;
+		  output: out integer range 0 to 131072
+	);
+end mux3216;
+
+architecture mux_arc of mux3216 is
+begin
+	process(rst, selektor, input1, input2)
+	begin
+	if(rst = '1') then
+		output <= 0; 
+	elsif selektor = '0' then
+		output <= input1; 
+	else
+		output <= input2;
+	end if;
+	end process;
+end mux_arc;