Skip to content

Commit

Permalink
Merge changes from topic "us_tc4_rebase_v2" into integration
Browse files Browse the repository at this point in the history 
* changes:
  feat(tc): bind DPU SMMU on TC4
  feat(tc): bind GPU SMMU on TC4
  feat(tc): update DT for Drage GPU
  feat(tc): enable SME and SME2 options for TC4
  feat(tc): add new TC4 RoS definitions
  feat(tc): add system generic timer register definition for TC4
  feat(tc): allow TARGET_VERSION=4
  feat(tc): add MHUv3 register addresses for TC4
  feat(tc): add device tree binding for TC4
  • Loading branch information
@ManishVB-Arm
ManishVB-Arm authored and TrustedFirmware Code Review committed Aug 29, 2024
2 parents 241ec3a + e365479 commit 8e9bdc5
Show file tree
Hide file tree
Showing 11 changed files with 260 additions and 108 deletions.
23 changes: 9 additions & 14 deletions fdts/tc-base.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -437,9 +437,9 @@

};

ethernet: ethernet@18000000 {
reg = <0x0 0x18000000 0x0 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
ethernet: ethernet@ETHERNET_ADDR {
reg = <0x0 ADDRESSIFY(ETHERNET_ADDR) 0x0 0x10000>;
interrupts = <GIC_SPI ETHERNET_INT IRQ_TYPE_LEVEL_HIGH 0>;

reg-io-width = <2>;
smsc,irq-push-pull;
Expand All @@ -452,10 +452,9 @@
clock-output-names = "bp:clock24mhz";
};


sysreg: sysreg@1c010000 {
sysreg: sysreg@SYS_REGS_ADDR {
compatible = "arm,vexpress-sysreg";
reg = <0x0 0x001c010000 0x0 0x1000>;
reg = <0x0 ADDRESSIFY(SYS_REGS_ADDR) 0x0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
};
Expand All @@ -468,11 +467,11 @@
regulator-always-on;
};

mmci: mmci@1c050000 {
mmci: mmci@MMC_ADDR {
compatible = "arm,pl180", "arm,primecell";
reg = <0x0 0x001c050000 0x0 0x1000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
reg = <0x0 ADDRESSIFY(MMC_ADDR) 0x0 0x1000>;
interrupts = <GIC_SPI MMC_INT_0 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI MMC_INT_1 IRQ_TYPE_LEVEL_HIGH 0>;
wp-gpios = <&sysreg 1 0>;
bus-width = <4>;
max-frequency = <25000000>;
Expand All @@ -496,10 +495,6 @@
gpu: gpu@2d000000 {
compatible = "arm,mali-midgard";
reg = <0x0 0x2d000000 0x0 0x200000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
clocks = <&gpu_core_clk>;
clock-names = "shadercores";
#if TC_SCMI_PD_CTRL_EN
Expand Down
4 changes: 2 additions & 2 deletions fdts/tc-fpga.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,12 +25,12 @@
stdout-path = "serial0:38400n8";
};

ethernet: ethernet@18000000 {
ethernet: ethernet@ETHERNET_ADDR {
compatible = "smsc,lan9115";
phy-mode = "mii";
};

mmci: mmci@1c050000 {
mmci: mmci@MMC_ADDR {
non-removable;
};
};
22 changes: 11 additions & 11 deletions fdts/tc-fvp.dtsi
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,26 +43,26 @@
stdout-path = "serial0:115200n8";
};

ethernet: ethernet@18000000 {
ethernet: ethernet@ETHERNET_ADDR {
compatible = "smsc,lan91c111";
};

mmci: mmci@1c050000 {
mmci: mmci@MMC_ADDR {
cd-gpios = <&sysreg 0 0>;
};

rtc@1c170000 {
rtc@RTC_ADDR {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x1C170000 0x0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
reg = <0x0 ADDRESSIFY(RTC_ADDR) 0x0 0x1000>;
interrupts = <GIC_SPI RTC_INT IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&soc_refclk>;
clock-names = "apb_pclk";
};

kmi@1c060000 {
kmi@KMI_0_ADDR {
compatible = "arm,pl050", "arm,primecell";
reg = <0x0 0x001c060000 0x0 0x1000>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
reg = <0x0 ADDRESSIFY(KMI_0_ADDR) 0x0 0x1000>;
interrupts = <GIC_SPI KMI_0_INT IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
clock-names = "KMIREFCLK", "apb_pclk";
};
Expand All @@ -75,10 +75,10 @@
clock-names = "KMIREFCLK", "apb_pclk";
};

virtio_block@1c130000 {
virtio_block@VIRTIO_BLOCK_ADDR {
compatible = "virtio,mmio";
reg = <0x0 0x1c130000 0x0 0x200>;
reg = <0x0 ADDRESSIFY(VIRTIO_BLOCK_ADDR) 0x0 0x200>;
/* spec lists this wrong */
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
interrupts = <GIC_SPI VIRTIO_BLOCK_INT IRQ_TYPE_LEVEL_HIGH 0>;
};
};
24 changes: 24 additions & 0 deletions fdts/tc2.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,26 @@
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69

#define ETHERNET_ADDR 18000000
#define ETHERNET_INT 109

#define SYS_REGS_ADDR 1c010000

#define MMC_ADDR 1c050000
#define MMC_INT_0 107
#define MMC_INT_1 108

#define RTC_ADDR 1c170000
#define RTC_INT 100

#define KMI_0_ADDR 1c060000
#define KMI_0_INT 197
#define KMI_1_ADDR 1c070000
#define KMI_1_INT 103

#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204

#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
Expand Down Expand Up @@ -271,6 +291,10 @@
};

gpu: gpu@2d000000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
iommus = <&smmu_700 0x200>;
};
};
84 changes: 84 additions & 0 deletions fdts/tc3-4-base.dtsi
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,84 @@
/*
* Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024

#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""

#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"

#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000

#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#include "tc-base.dtsi"

/ {
cpus {
CPU2:cpu@200 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};

CPU3:cpu@300 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};

CPU6:cpu@600 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};

CPU7:cpu@700 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
};

gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};

ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};

ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};

sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};

firmware {
scmi {
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
};
97 changes: 23 additions & 74 deletions fdts/tc3.dts
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,67 +10,42 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <platform_def.h>

#define LIT_CAPACITY 239
#define MID_CAPACITY 686
#define BIG_CAPACITY 1024

#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_TX_COMPAT "arm,mhuv3"
#define MHU_TX_INT_NAME ""

#define MHU_RX_ADDR 46140000 /* hex */
#define MHU_RX_COMPAT "arm,mhuv3"
#define MHU_OFFSET 0x10000
#define MHU_MBOX_CELLS 3
#define MHU_RX_INT_NUM 300
#define MHU_RX_INT_NAME "combined-mbx"

#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"

#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
#define UARTCLK_FREQ 3750000
#define ETHERNET_ADDR 18000000
#define ETHERNET_INT 109

#if TARGET_FLAVOUR_FVP
#define DPU_ADDR 4000000000
#define DPU_IRQ 579
#elif TARGET_FLAVOUR_FPGA
#define DPU_ADDR 2cc00000
#define DPU_IRQ 69
#endif
#define SYS_REGS_ADDR 1c010000

#define MMC_ADDR 1c050000
#define MMC_INT_0 107
#define MMC_INT_1 108

#define RTC_ADDR 1c170000
#define RTC_INT 100

#define KMI_0_ADDR 1c060000
#define KMI_0_INT 197
#define KMI_1_ADDR 1c070000
#define KMI_1_INT 103

#define VIRTIO_BLOCK_ADDR 1c130000
#define VIRTIO_BLOCK_INT 204

#include "tc-common.dtsi"
#if TARGET_FLAVOUR_FVP
#include "tc-fvp.dtsi"
#else
#include "tc-fpga.dtsi"
#endif /* TARGET_FLAVOUR_FVP */
#include "tc-base.dtsi"
#include "tc3-4-base.dtsi"

/ {
cpus {
CPU2:cpu@200 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};

CPU3:cpu@300 {
clocks = <&scmi_dvfs 1>;
capacity-dmips-mhz = <MID_CAPACITY>;
};

CPU6:cpu@600 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};

CPU7:cpu@700 {
clocks = <&scmi_dvfs 2>;
capacity-dmips-mhz = <BIG_CAPACITY>;
};
};

cs-pmu@0 {
compatible = "arm,coresight-pmu";
reg = <0x0 MCN_PMU_ADDR(0) 0x0 0xffc>;
Expand Down Expand Up @@ -109,36 +84,6 @@
reg = <0x0 0x4f000000 0x0 0x4000000>;
};

sram: sram@6000000 {
cpu_scp_scmi_p2a: scp-shmem@80 {
compatible = "arm,scmi-shmem";
reg = <0x80 0x80>;
};
};

firmware {
scmi {
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};

gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
affinity = <&CPU0>, <&CPU1>;
};

ppi_partition_mid: interrupt-partition-1 {
affinity = <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
};

ppi_partition_big: interrupt-partition-2 {
affinity = <&CPU6>, <&CPU7>;
};
};
};

#if TARGET_FLAVOUR_FVP
smmu_700: iommu@3f000000 {
status = "okay";
Expand All @@ -165,6 +110,10 @@
};

gpu: gpu@2d000000 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "JOB", "MMU", "GPU";
#if TARGET_FLAVOUR_FVP
iommus = <&smmu_700 0x200>;
#endif
Expand Down
Loading

0 comments on commit 8e9bdc5

Please sign in to comment.