Fix issues when trying to parameterize Verilog modules

[piotrva]

This fixes #944 by trying to execute an original version (case-insensitive for VHDL compatibility) with the fall-back for use with Verilog and non-lower-case module names.

[piotrva]

Hi, any chance for having someone look at this PR?
We use VUnit in our company and for now we had to switch to my unofficial branch.

[oscargus]

I think it maybe is better to either:

1. Move the case-handling to get_test_bench
2. Do try-except on get_test_bench only and then only check KeyError.

[piotrva]

@oscargus I modified it as you suggested.

[oscargus]

Thanks! (I should probably have mentioned that I cannot approve or merge anything, but I think/hope that the suggested changes increases the chance of having it merged...)

[piotrva]

Can you possibly contact someone who is in charge of such approvals?
This issue is preventing us for use of official VUnit repo in our workflow what is suboptimal at least...

[oscargus]

I can try to ping in @LarsAsplund and @kraigher . My impression is that they have been quite busy recently though. (There may be other people that have the correct powers as well.)

[piotrva]

Any chance to have this fix merged any time soon?

[piotrva]

More than a year passed - is this repository still maintained somehow?

[LarsAsplund]

@piotrva Sorry for the delay. VUnit has a lot of users, which is good, but unfortunately we don't have maintainer bandwidth to meet that. Working on solutions...

Regarding your PR. First of all, all tests must be green for a PR to pass. Not sure why they went red the last time since the logs are deleted when they get too old.

I would also recommend a solution that doesn't involve code related to VHDL as this is a Verilog issue. What I recommend is that you don't let module call test_bench but rather let it return what test_bench returns, thereby avoiding the name = name.lower() call.

Provided the all tests pass after this change, there should also be a test covering this issue. I would recommend looking into tests/acceptance/artificial/verilog/ to see if those tests can be extended to include this casing issue

[piotrva]

Hi, thanks for the response - is there a way the tests can be run again so I can see logs?

[LarsAsplund]

@piotrva You can run all the tests locally, see https://vunit.github.io/contributing.html. However, if you do the update I suggested and push that, the CI will start and run the tests (I may have to approve the run first). After that the logs are visible. Make sure that you rebase your change on the HEAD of VUnit.