Merge pull request #4627 from RCoeurjoly/roland/assume_x

YosysHQ · Nov 6, 2024 · 9068ec5 · 9068ec5
2 parents 2de24dc + 5ea2c6e
commit 9068ec5
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Showing 4 changed files with 26 additions and 2 deletions.
diff --git a/kernel/fstdata.cc b/kernel/fstdata.cc
@@ -258,7 +258,8 @@ void FstData::reconstructAllAtTimes(std::vector<fstHandle> &signal, uint64_t sta
 
 std::string FstData::valueOf(fstHandle signal)
 {
-	if (past_data.find(signal) == past_data.end())
-		log_error("Signal id %d not found\n", (int)signal);
+	if (past_data.find(signal) == past_data.end()) {
+		return std::string(handle_to_var[signal].width, 'x');
+	}
 	return past_data[signal];
 }
diff --git a/tests/sim/assume_x_first_step.ys b/tests/sim/assume_x_first_step.ys
@@ -0,0 +1,2 @@
+read_verilog simple_assign.v
+sim -r simple_assign.vcd -scope simple_assign
diff --git a/tests/sim/simple_assign.v b/tests/sim/simple_assign.v
@@ -0,0 +1,8 @@
+module simple_assign (
+    input wire in,
+    output wire out
+);
+
+    assign out = in;
+
+endmodule
diff --git a/tests/sim/simple_assign.vcd b/tests/sim/simple_assign.vcd
@@ -0,0 +1,13 @@
+$version Yosys $end
+$scope module simple_assign $end
+$var wire 1 n2 in $end
+$var wire 1 n1 out $end
+$upscope $end
+$enddefinitions $end
+#0
+#5
+b1 n1
+b1 n2
+#10
+b0 n1
+b0 n2
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1,2 @@
		read_verilog simple_assign.v
		sim -r simple_assign.vcd -scope simple_assign