afzalamu / 8Bit-signed-Full-Adder-on-ARTIX-7-FPGA Public

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Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.

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Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
README.md		README.md
addertop.v		addertop.v
addertop_tb.v		addertop_tb.v
myxdcfile1.xdc		myxdcfile1.xdc
reg8bit.v		reg8bit.v
signedadder.v		signedadder.v

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8 Bit Signed Full Adder

VERILOG CODE

RTL SCHEMATIC

TESTBENCH

SIMULATION RESULTS

HARDWARE IMPLEMENTATION RESULTS

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Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.

fpga verilog full-adder verilog-project artix-7 fpga-projects

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