GitHub - baowendin/pipeline-cpu: ZheJiang University Project

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 30 Commits
PCPU		PCPU
ipcore_dir		ipcore_dir
isim		isim
.gitignore		.gitignore
ALU.sym		ALU.sym
Counter_3_IO.v		Counter_3_IO.v
DispNum.jhd		DispNum.jhd
DispNum.sch		DispNum.sch
DispNum.sym		DispNum.sym
DispNum.vf		DispNum.vf
Display.jhd		Display.jhd
Display.sch		Display.sch
Display.sym		Display.sym
Display.vf		Display.vf
ExtNew.sym		ExtNew.sym
ExtNew.v		ExtNew.v
Ext_32.sym		Ext_32.sym
Ext_32.v		Ext_32.v
GPIO.sym		GPIO.sym
GPIO.v		GPIO.v
HexTo8SEG.sym		HexTo8SEG.sym
HexTo8SEG.v		HexTo8SEG.v
INST_ROM.txt		INST_ROM.txt
LEDP2S_IO.v		LEDP2S_IO.v
MC14495_ZJU.jhd		MC14495_ZJU.jhd
MC14495_ZJU.sch		MC14495_ZJU.sch
MC14495_ZJU.sym		MC14495_ZJU.sym
MC14495_ZJU.vf		MC14495_ZJU.vf
MIO_BUS_IO.v		MIO_BUS_IO.v
MUX2T1_32.sym		MUX2T1_32.sym
MUX2T1_32.v		MUX2T1_32.v
MUX2T1_64.sym		MUX2T1_64.sym
MUX2T1_64.v		MUX2T1_64.v
MUX2T1_8.sym		MUX2T1_8.sym
MUX2T1_8.v		MUX2T1_8.v
MUX4T1_32.sym		MUX4T1_32.sym
MUX4T1_32.v		MUX4T1_32.v
MUX4T1_5.sym		MUX4T1_5.sym
MUX4T1_5.v		MUX4T1_5.v
MUX8T1_32.v		MUX8T1_32.v
MUX8T1_8.v		MUX8T1_8.v
M_datapath.jhd		M_datapath.jhd
M_datapath.sch		M_datapath.sch
M_datapath.schbak		M_datapath.schbak
M_datapath.vf		M_datapath.vf
Multi_8CH32.sym		Multi_8CH32.sym
Multi_8CH32.v		Multi_8CH32.v
OExp09.xise		OExp09.xise
OExp09_top.v		OExp09_top.v
P2S.sym		P2S.sym
P2S_IO.v		P2S_IO.v
PCPU.jhd		PCPU.jhd
PCPU_sim_isim_beh.exe		PCPU_sim_isim_beh.exe
PCPU_sim_isim_beh.wdb		PCPU_sim_isim_beh.wdb
PCPU_sim_isim_beh1.wdb		PCPU_sim_isim_beh1.wdb
PIO_IO.v		PIO_IO.v
RAM_B.mif		RAM_B.mif
REG32.sym		REG32.sym
REG32.v		REG32.v
ROM_B.mif		ROM_B.mif
SAnti_jitter_IO.v		SAnti_jitter_IO.v
SEnter_2_32_IO.v		SEnter_2_32_IO.v
SOC-Sword.ucf		SOC-Sword.ucf
SSeg_map.sym		SSeg_map.sym
SSeg_map.v		SSeg_map.v
ScanSync.sym		ScanSync.sym
ScanSync.v		ScanSync.v
Seg_map.sym		Seg_map.sym
Seg_map.v		Seg_map.v
ShiftLeft_2.bmm		ShiftLeft_2.bmm
ShiftLeft_2.sym		ShiftLeft_2.sym
ShiftLeft_2.v		ShiftLeft_2.v
clk_diff.v		clk_diff.v
clk_div.sym		clk_div.sym
clk_div.v		clk_div.v
ctrl - Copy.v		ctrl - Copy.v
ctrl.v		ctrl.v
data_mem.hex		data_mem.hex
fuse.log		fuse.log
fuse.xmsgs		fuse.xmsgs
fuseRelaunch.cmd		fuseRelaunch.cmd
isim.cmd		isim.cmd
isim.log		isim.log
regs.sym		regs.sym
sch2HdlBatchFile		sch2HdlBatchFile
xilinxsim.ini		xilinxsim.ini