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PPCRec: Clean up some outdated code
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@Exzap
Exzap committed Oct 26, 2024
1 parent 636b63f commit 126a682
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Showing 5 changed files with 45 additions and 114 deletions.
74 changes: 35 additions & 39 deletions src/Cafe/HW/Espresso/Recompiler/IML/IMLInstruction.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,13 +18,9 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
registersUsed->readGPR1 = IMLREG_INVALID;
registersUsed->readGPR2 = IMLREG_INVALID;
registersUsed->readGPR3 = IMLREG_INVALID;
registersUsed->readGPR4 = IMLREG_INVALID;
registersUsed->writtenGPR1 = IMLREG_INVALID;
registersUsed->writtenGPR2 = IMLREG_INVALID;
registersUsed->readFPR1 = IMLREG_INVALID;
registersUsed->readFPR2 = IMLREG_INVALID;
registersUsed->readFPR3 = IMLREG_INVALID;
registersUsed->readFPR4 = IMLREG_INVALID;
registersUsed->writtenFPR1 = IMLREG_INVALID;
if (type == PPCREC_IML_TYPE_R_NAME)
{
registersUsed->writtenGPR1 = op_r_name.regR;
Expand Down Expand Up @@ -243,7 +239,7 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
else if (type == PPCREC_IML_TYPE_FPR_LOAD)
{
// fpr load operation
registersUsed->writtenFPR1 = op_storeLoad.registerData;
registersUsed->writtenGPR1 = op_storeLoad.registerData;
// address is in gpr register
if (op_storeLoad.registerMem.IsValid())
registersUsed->readGPR1 = op_storeLoad.registerMem;
Expand All @@ -257,8 +253,8 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
break;
case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
// PS1 remains the same
registersUsed->readFPR4 = op_storeLoad.registerData;
cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
registersUsed->readGPR2 = op_storeLoad.registerData;
break;
case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1:
case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1:
Expand All @@ -280,7 +276,7 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
else if (type == PPCREC_IML_TYPE_FPR_LOAD_INDEXED)
{
// fpr load operation
registersUsed->writtenFPR1 = op_storeLoad.registerData;
registersUsed->writtenGPR1 = op_storeLoad.registerData;
// address is in gpr registers
if (op_storeLoad.registerMem.IsValid())
registersUsed->readGPR1 = op_storeLoad.registerMem;
Expand All @@ -297,7 +293,7 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
case PPCREC_FPR_LD_MODE_DOUBLE_INTO_PS0:
// PS1 remains the same
cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
registersUsed->readFPR4 = op_storeLoad.registerData;
registersUsed->readGPR3 = op_storeLoad.registerData;
break;
case PPCREC_FPR_LD_MODE_SINGLE_INTO_PS0_PS1:
case PPCREC_FPR_LD_MODE_PSQ_FLOAT_PS0_PS1:
Expand All @@ -318,16 +314,16 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
else if (type == PPCREC_IML_TYPE_FPR_STORE)
{
// fpr store operation
registersUsed->readFPR1 = op_storeLoad.registerData;
registersUsed->readGPR1 = op_storeLoad.registerData;
if (op_storeLoad.registerMem.IsValid())
registersUsed->readGPR1 = op_storeLoad.registerMem;
registersUsed->readGPR2 = op_storeLoad.registerMem;
// PSQ generic stores also access GQR
switch (op_storeLoad.mode)
{
case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0:
case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1:
cemu_assert_debug(op_storeLoad.registerGQR.IsValid());
registersUsed->readGPR2 = op_storeLoad.registerGQR;
registersUsed->readGPR3 = op_storeLoad.registerGQR;
break;
default:
cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
Expand All @@ -337,19 +333,19 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
else if (type == PPCREC_IML_TYPE_FPR_STORE_INDEXED)
{
// fpr store operation
registersUsed->readFPR1 = op_storeLoad.registerData;
registersUsed->readGPR1 = op_storeLoad.registerData;
// address is in gpr registers
if (op_storeLoad.registerMem.IsValid())
registersUsed->readGPR1 = op_storeLoad.registerMem;
registersUsed->readGPR2 = op_storeLoad.registerMem;
if (op_storeLoad.registerMem2.IsValid())
registersUsed->readGPR2 = op_storeLoad.registerMem2;
registersUsed->readGPR3 = op_storeLoad.registerMem2;
// PSQ generic stores also access GQR
switch (op_storeLoad.mode)
{
case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0:
case PPCREC_FPR_ST_MODE_PSQ_GENERIC_PS0_PS1:
cemu_assert_debug(op_storeLoad.registerGQR.IsValid());
registersUsed->readGPR3 = op_storeLoad.registerGQR;
registersUsed->readGPR4 = op_storeLoad.registerGQR;
break;
default:
cemu_assert_debug(op_storeLoad.registerGQR.IsInvalid());
Expand All @@ -369,8 +365,8 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
operation == PPCREC_IML_OP_FPR_FRSQRTE_PAIR)
{
// operand read, result written
registersUsed->readFPR1 = op_fpr_r_r.regA;
registersUsed->writtenFPR1 = op_fpr_r_r.regR;
registersUsed->readGPR1 = op_fpr_r_r.regA;
registersUsed->writtenGPR1 = op_fpr_r_r.regR;
}
else if (
operation == PPCREC_IML_OP_FPR_COPY_BOTTOM_TO_BOTTOM ||
Expand All @@ -383,9 +379,9 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
)
{
// operand read, result read and (partially) written
registersUsed->readFPR1 = op_fpr_r_r.regA;
registersUsed->readFPR4 = op_fpr_r_r.regR;
registersUsed->writtenFPR1 = op_fpr_r_r.regR;
registersUsed->readGPR1 = op_fpr_r_r.regA;
registersUsed->readGPR2 = op_fpr_r_r.regR;
registersUsed->writtenGPR1 = op_fpr_r_r.regR;
}
else if (operation == PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM ||
operation == PPCREC_IML_OP_FPR_MULTIPLY_PAIR ||
Expand All @@ -397,35 +393,35 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
operation == PPCREC_IML_OP_FPR_SUB_BOTTOM)
{
// operand read, result read and written
registersUsed->readFPR1 = op_fpr_r_r.regA;
registersUsed->readFPR2 = op_fpr_r_r.regR;
registersUsed->writtenFPR1 = op_fpr_r_r.regR;
registersUsed->readGPR1 = op_fpr_r_r.regA;
registersUsed->readGPR2 = op_fpr_r_r.regR;
registersUsed->writtenGPR1 = op_fpr_r_r.regR;

}
else if (operation == PPCREC_IML_OP_FPR_FCMPU_BOTTOM ||
operation == PPCREC_IML_OP_FPR_FCMPU_TOP ||
operation == PPCREC_IML_OP_FPR_FCMPO_BOTTOM)
{
// operand read, result read
registersUsed->readFPR1 = op_fpr_r_r.regA;
registersUsed->readFPR2 = op_fpr_r_r.regR;
registersUsed->readGPR1 = op_fpr_r_r.regA;
registersUsed->readGPR2 = op_fpr_r_r.regR;
}
else
cemu_assert_unimplemented();
}
else if (type == PPCREC_IML_TYPE_FPR_R_R_R)
{
// fpr operation
registersUsed->readFPR1 = op_fpr_r_r_r.regA;
registersUsed->readFPR2 = op_fpr_r_r_r.regB;
registersUsed->writtenFPR1 = op_fpr_r_r_r.regR;
registersUsed->readGPR1 = op_fpr_r_r_r.regA;
registersUsed->readGPR2 = op_fpr_r_r_r.regB;
registersUsed->writtenGPR1 = op_fpr_r_r_r.regR;
// handle partially written result
switch (operation)
{
case PPCREC_IML_OP_FPR_MULTIPLY_BOTTOM:
case PPCREC_IML_OP_FPR_ADD_BOTTOM:
case PPCREC_IML_OP_FPR_SUB_BOTTOM:
registersUsed->readFPR4 = op_fpr_r_r_r.regR;
registersUsed->readGPR3 = op_fpr_r_r_r.regR;
break;
case PPCREC_IML_OP_FPR_SUB_PAIR:
break;
Expand All @@ -436,15 +432,15 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
else if (type == PPCREC_IML_TYPE_FPR_R_R_R_R)
{
// fpr operation
registersUsed->readFPR1 = op_fpr_r_r_r_r.regA;
registersUsed->readFPR2 = op_fpr_r_r_r_r.regB;
registersUsed->readFPR3 = op_fpr_r_r_r_r.regC;
registersUsed->writtenFPR1 = op_fpr_r_r_r_r.regR;
registersUsed->readGPR1 = op_fpr_r_r_r_r.regA;
registersUsed->readGPR2 = op_fpr_r_r_r_r.regB;
registersUsed->readGPR3 = op_fpr_r_r_r_r.regC;
registersUsed->writtenGPR1 = op_fpr_r_r_r_r.regR;
// handle partially written result
switch (operation)
{
case PPCREC_IML_OP_FPR_SELECT_BOTTOM:
registersUsed->readFPR4 = op_fpr_r_r_r_r.regR;
registersUsed->readGPR4 = op_fpr_r_r_r_r.regR;
break;
case PPCREC_IML_OP_FPR_SUM0:
case PPCREC_IML_OP_FPR_SUM1:
Expand All @@ -464,17 +460,17 @@ void IMLInstruction::CheckRegisterUsage(IMLUsedRegisters* registersUsed) const
operation == PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_BOTTOM ||
operation == PPCREC_IML_OP_FPR_ROUND_TO_SINGLE_PRECISION_PAIR)
{
registersUsed->readFPR1 = op_fpr_r.regR;
registersUsed->writtenFPR1 = op_fpr_r.regR;
registersUsed->readGPR1 = op_fpr_r.regR;
registersUsed->writtenGPR1 = op_fpr_r.regR;
}
else
cemu_assert_unimplemented();
}
else if (type == PPCREC_IML_TYPE_FPR_COMPARE)
{
registersUsed->writtenGPR1 = op_fpr_compare.regR;
registersUsed->readFPR1 = op_fpr_compare.regA;
registersUsed->readFPR2 = op_fpr_compare.regB;
registersUsed->readGPR1 = op_fpr_compare.regA;
registersUsed->readGPR2 = op_fpr_compare.regB;
}
else if (type == PPCREC_IML_TYPE_X86_EFLAGS_JCC)
{
Expand Down
62 changes: 5 additions & 57 deletions src/Cafe/HW/Espresso/Recompiler/IML/IMLInstruction.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -335,31 +335,18 @@ struct IMLUsedRegisters
{
IMLUsedRegisters() {};

// GPR
union
{
struct
{
IMLReg readGPR1;
IMLReg readGPR2;
IMLReg readGPR3;
IMLReg readGPR4;
IMLReg writtenGPR1;
IMLReg writtenGPR2;
};
};
// FPR
union
{
struct
{
// note: If destination operand is not fully written (PS0 and PS1) it will be added to the read registers
IMLReg readFPR1;
IMLReg readFPR2;
IMLReg readFPR3;
IMLReg readFPR4;
IMLReg writtenFPR1;
};
};

bool IsWrittenByRegId(IMLRegID regId) const
{
Expand All @@ -377,17 +364,6 @@ struct IMLUsedRegisters
return IsWrittenByRegId(regId);
}

bool IsRegIdRead(IMLRegID regId) const
{
if (readGPR1.IsValid() && readGPR1.GetRegID() == regId)
return true;
if (readGPR2.IsValid() && readGPR2.GetRegID() == regId)
return true;
if (readGPR3.IsValid() && readGPR3.GetRegID() == regId)
return true;
return false;
}

template<typename Fn>
void ForEachWrittenGPR(Fn F) const
{
Expand All @@ -406,27 +382,8 @@ struct IMLUsedRegisters
F(readGPR2);
if (readGPR3.IsValid())
F(readGPR3);
}

// temporary (for FPRs)
template<typename Fn>
void ForEachWrittenFPR(Fn F) const
{
if (writtenFPR1.IsValid())
F(writtenFPR1);
}

template<typename Fn>
void ForEachReadFPR(Fn F) const
{
if (readFPR1.IsValid())
F(readFPR1);
if (readFPR2.IsValid())
F(readFPR2);
if (readFPR3.IsValid())
F(readFPR3);
if (readFPR4.IsValid())
F(readFPR4);
if (readGPR4.IsValid())
F(readGPR4);
}

template<typename Fn>
Expand All @@ -439,21 +396,12 @@ struct IMLUsedRegisters
F(readGPR2, false);
if (readGPR3.IsValid())
F(readGPR3, false);
if (readGPR4.IsValid())
F(readGPR4, false);
if (writtenGPR1.IsValid())
F(writtenGPR1, true);
if (writtenGPR2.IsValid())
F(writtenGPR2, true);
// FPRs
if (readFPR1.IsValid())
F(readFPR1, false);
if (readFPR2.IsValid())
F(readFPR2, false);
if (readFPR3.IsValid())
F(readFPR3, false);
if (readFPR4.IsValid())
F(readFPR4, false);
if (writtenFPR1.IsValid())
F(writtenFPR1, true);
}

};
Expand Down
10 changes: 5 additions & 5 deletions src/Cafe/HW/Espresso/Recompiler/IML/IMLOptimizer.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,15 +57,15 @@ void PPCRecompiler_optimizeDirectFloatCopiesScanForward(ppcImlGenContext_t* ppcI

// check if FPR is overwritten (we can actually ignore read operations?)
imlInstruction->CheckRegisterUsage(&registersUsed);
if (registersUsed.writtenFPR1.IsValidAndSameRegID(fprIndex))
if (registersUsed.writtenGPR1.IsValidAndSameRegID(fprIndex) || registersUsed.writtenGPR2.IsValidAndSameRegID(fprIndex))
break;
if (registersUsed.readFPR1.IsValidAndSameRegID(fprIndex))
if (registersUsed.readGPR1.IsValidAndSameRegID(fprIndex))
break;
if (registersUsed.readFPR2.IsValidAndSameRegID(fprIndex))
if (registersUsed.readGPR2.IsValidAndSameRegID(fprIndex))
break;
if (registersUsed.readFPR3.IsValidAndSameRegID(fprIndex))
if (registersUsed.readGPR3.IsValidAndSameRegID(fprIndex))
break;
if (registersUsed.readFPR4.IsValidAndSameRegID(fprIndex))
if (registersUsed.readGPR4.IsValidAndSameRegID(fprIndex))
break;
}

Expand Down
10 changes: 0 additions & 10 deletions src/Cafe/HW/Espresso/Recompiler/IML/IMLRegisterAllocator.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1502,22 +1502,12 @@ void IMLRA_ConvertAbstractToLivenessRanges(IMLRegisterAllocatorContext& ctx, IML
raLivenessRange* subrange = regToSubrange.find(gprId)->second;
IMLRA_UpdateOrAddSubrangeLocation(subrange, pos);
});
gprTracking.ForEachReadFPR([&](IMLReg gprReg) {
IMLRegID gprId = gprReg.GetRegID();
raLivenessRange* subrange = regToSubrange.find(gprId)->second;
IMLRA_UpdateOrAddSubrangeLocation(subrange, pos);
});
pos = {(sint32)index, false};
gprTracking.ForEachWrittenGPR([&](IMLReg gprReg) {
IMLRegID gprId = gprReg.GetRegID();
raLivenessRange* subrange = regToSubrange.find(gprId)->second;
IMLRA_UpdateOrAddSubrangeLocation(subrange, pos);
});
gprTracking.ForEachWrittenFPR([&](IMLReg gprReg) {
IMLRegID gprId = gprReg.GetRegID();
raLivenessRange* subrange = regToSubrange.find(gprId)->second;
IMLRA_UpdateOrAddSubrangeLocation(subrange, pos);
});
// check fixed register requirements
IMLFixedRegisters fixedRegs;
GetInstructionFixedRegisters(&imlSegment->imlList[index], fixedRegs);
Expand Down
3 changes: 0 additions & 3 deletions src/Cafe/HW/Espresso/Recompiler/PPCRecompiler.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -334,9 +334,6 @@ bool PPCRecompiler_ApplyIMLPasses(ppcImlGenContext_t& ppcImlGenContext)

PPCRecompiler_NativeRegisterAllocatorPass(ppcImlGenContext);

//PPCRecompiler_reorderConditionModifyInstructions(&ppcImlGenContext);
//PPCRecompiler_removeRedundantCRUpdates(&ppcImlGenContext);

return true;
}

Expand Down

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