Remove latch from bus_rx_flow logic

Internal-tag: [#71746]
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

src/ctrl/bus_rx_flow.sv

@@ -79,11 +79,9 @@ module bus_rx_flow (
   end
 
   always_comb begin : update_output_data_value
-    if (~rst_ni) begin
-      rx_data_o = '0;
-    end else if (rx_req_bit) begin
+    if (rx_req_bit) begin
       rx_data_o = {{7{1'b0}}, rx_bit};
-    end else if (rx_req_byte_i) begin
+    end else begin
       rx_data_o = {rx_data[6:0], sda_i};
     end
   end

verification/cocotb/block/bus_rx_flow/test_bus_rx_flow.py

@@ -51,7 +51,6 @@ async def setup_test(dut):
     await ClockCycles(dut.clk_i, 10)
 
     assert dut.rx_done_o.value == 0
-    assert dut.rx_data_o.value == 0
     assert dut.rx_idle_o.value == 1
 
 
@@ -74,6 +73,7 @@ async def test_multiple_bit_reads(dut):
         result = await First(scl_negedge, done_posedge)
 
         if result == done_posedge:
+            await RisingEdge(dut.clk_i)
             assert dut.rx_data_o.value == d
             dut.rx_req_bit_i.value = 0
             dut._log.debug(f"Bit correct, rx_data_o: {dut.rx_data_o.value}, expected: {d}")