axi_adapter_wrapper: make 8 bit wstrb

chipsalliance · Dec 18, 2024 · b007e0b · b007e0b
1 parent 8b7227f
commit b007e0b
Showing 1 changed file with 5 additions and 2 deletions.
diff --git a/verification/cocotb/block/axi_adapter/axi_adapter_wrapper.sv b/verification/cocotb/block/axi_adapter/axi_adapter_wrapper.sv
@@ -50,7 +50,7 @@ module axi_adapter_wrapper
     output logic                    awready,
 
     input  logic [AxiDataWidth-1:0] wdata,
-    input  logic [             7:0] wstrb,
+    input  logic [             3:0] wstrb,
     input  logic                    wlast,
     input  logic                    wvalid,
     output logic                    wready,
@@ -73,6 +73,9 @@ module axi_adapter_wrapper
   logic [CsrDataWidth-1:0] s_cpuif_rd_data;
   logic                    s_cpuif_wr_ack;
   logic                    s_cpuif_wr_err;
+  logic                    wstrb_i;
+
+  assign wstrb_i = {4'b0000, wstrb};
 
   axi_adapter #(
       .AxiDataWidth(AxiDataWidth),
@@ -113,7 +116,7 @@ module axi_adapter_wrapper
       .awready_o(awready),
 
       .wdata_i (wdata),
-      .wstrb_i (wstrb),
+      .wstrb_i (wstrb_i),
       .wlast_i (wlast),
       .wvalid_i(wvalid),
       .wready_o(wready),