fifo register (not available on UART8250)

devse-org · Feb 15, 2023 · b7c2c8c · b7c2c8c
1 parent 3eb6513
commit b7c2c8c
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/src/périphériques/communication-serie/UART8250.md b/src/périphériques/communication-serie/UART8250.md
@@ -1,4 +1,4 @@
-# UART8250 / UART16750
+# UART8250 / UART16550
 
 <div align="center">
 
@@ -13,6 +13,7 @@
 | 0x0 (DLAB == 0)  | Transmit Holding Register (THR)         | ✔️        | ❌     |
 | 0x0 (DLAB == 0)  | Receive Buffer Register (RBR)           | ❌        | ✔️     |
 | 0x1 (DLAB == 0)  | Interrupt Enable Register (IER)         | ✔️        | ✔️     |
+| 0x2 (⚠️UART16550 seulement) | FIFO Control Register (FCR)             | ✔️        | ❌     |
 | 0x2              | Interrupt Identification Register (IIR) | ❌        | ✔️     |
 | 0x3              | Line Control Register (LCR)             | ✔️        | ✔️     |
 | 0x4              | Modem Control Register (MCR)            | ✔️        | ✔️     |
@@ -99,4 +100,5 @@ Partons du principe que nous avont `uart8250_write` permetant d'ecrire une valeu
 
 ## Références
 
-- [Datasheet](https://web.archive.org/web/20160503070506/http://archive.pcjs.org/pubs/pc/datasheets/8250A-UART.pdf)
+- [8250A UART datasheet](https://web.archive.org/web/20160503070506/http://archive.pcjs.org/pubs/pc/datasheets/8250A-UART.pdf)
+- [PC16550D UART datasheet](https://web.archive.org/web/20180826215135/http://www.ti.com/lit/ds/symlink/pc16550d.pdf)