uart8250: add IIR and LCR

devse-org · Feb 15, 2023 · ddeeb8d · ddeeb8d
1 parent 5b51f42
commit ddeeb8d
Showing 1 changed file with 9 additions and 1 deletion.
diff --git a/src/périphériques/communication-serie/UART8250.md b/src/périphériques/communication-serie/UART8250.md
@@ -13,7 +13,7 @@
 | 0x0 (DLAB == 0)  | Transmit Holding Register (THR)         | ✔️        | ❌     |
 | 0x0 (DLAB == 0)  | Receive Buffer Register (RBR)           | ❌        | ✔️     |
 | 0x1 (DLAB == 0)  | Interrupt Enable Register (IER)         | ✔️        | ✔️     |
-| 0x2 (⚠️UART16550 seulement) | FIFO Control Register (FCR)             | ✔️        | ❌     |
+| 0x2 (⚠️UART16550 seulement) | FIFO Control Register (FCR)  | ✔️        | ❌     |
 | 0x2              | Interrupt Identification Register (IIR) | ❌        | ✔️     |
 | 0x3              | Line Control Register (LCR)             | ✔️        | ✔️     |
 | 0x4              | Modem Control Register (MCR)            | ✔️        | ✔️     |
@@ -42,8 +42,16 @@ Tout ce qui est reçu par l'UART sur la laison série sera accessible sur ce reg
 
 ### Interrupt Identification Register (IIR)
 
+| 7-3     | 2-1          | 0                 |
+|---------|--------------|-------------------|
+| reservé | Interrupt ID | Interrupt pending |
+
 ### Line Control Register (LCR)
 
+| 7    | 6         | 5            | 4                  | 3             | 2         | 1-0             |
+|------|-----------|--------------|--------------------|---------------|-----------|-----------------|
+| DLAB | Set Break | Stick parity | Even Parity Select | Parity enable | Stop Bits | Word length     |
+
 ### Modem Control Register (MCR)
 
 ### Line Status Register (LSR)