Jit: Fix "skip redundant flushes" for skipped instructions #13261
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Normally when an instruction is skipped (for instance due to branch merging or the BLR optimization), the registers that would have been flushed at the end of that instruction will instead be flushed at the end of the next instruction, which is maybe not perfect, but usually good enough. However, since the addition of the "skip redundant flushes" logic in fd511a6, Dolphin has accidentally skipped flushing those registers, which creates unnecessary register pressure. This commit restores the old behavior.
Now we no longer have to wait until we've compiled the next instruction after a skipped instruction before we can flush registers. This commit is easier to read using "Ignore whitespace".
This was technically wrong, but it only affected merged dcbt+dcbst, and I doubt any games care about it.
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Normally when an instruction is skipped (for instance due to branch merging or the BLR optimization), the registers that would have been flushed at the end of that instruction will instead be flushed at the end of the next instruction, which is maybe not perfect, but usually good enough. However, since the addition of the "skip redundant flushes" logic in fd511a6, Dolphin has accidentally skipped flushing those registers, which creates unnecessary register pressure.
The first commit of this pull request restores the old behavior. I also have two extra commits that improve things further.