feat: add SYNTH_CORNER

Signed-off-by: Kareem Farid <kareefardi@users.noreply.github.com>
efabless · Jan 2, 2025 · 3c25250 · 3c25250
1 parent 2400723
commit 3c25250
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Showing 5 changed files with 8 additions and 5 deletions.
diff --git a/Changelog.md b/Changelog.md
@@ -18,6 +18,9 @@
 
 ## Steps
 
+* `Yosys.*`
+  * Added `SYNTH_CORNER`
+
 * `OpenROAD.CTS`
   * Added flags `CTS_OBSTRUCTION_AWARE` and `CTS_BALANCE_LEVELS`
   * Added `CTS_SINK_BUFFER_MAX_CAP_DERATE_PCT`

diff --git a/openlane/common/toolbox.py b/openlane/common/toolbox.py
@@ -91,7 +91,7 @@ def filter_views(
             corner.
         :param views_by_corner: The mapping from (wild cards) of corner names to
             views.
-        :param corner: An explicit override for the default corner. Must be a
+        :param timing_corner: An explicit override for the default corner. Must be a
             fully qualified IPVT corner.
         :returns: The created list
         """

diff --git a/openlane/config/pdk_compat.py b/openlane/config/pdk_compat.py
@@ -214,7 +214,6 @@ def process_sta(key: str):
                 "max_ss_100C_1v60",
                 "max_ff_n40C_1v95",
             ]
-            new["SYNTH_CORNER"] = "*_ss_100C_1v60"
         elif new["PDK"].startswith("gf180mcu"):
             new["STA_CORNERS"] = [
                 "nom_tt_025C_5v00",
@@ -227,7 +226,6 @@ def process_sta(key: str):
                 "max_ss_125C_4v50",
                 "max_ff_n40C_5v50",
             ]
-            new["SYNTH_CORNER"] = "*_ss_125C_4v50"
 
         new["DEFAULT_CORNER"] = f"nom_{default_pvt}"
         new["TIMING_VIOLATION_CORNERS"] = ["*tt*"]

diff --git a/openlane/steps/pyosys.py b/openlane/steps/pyosys.py
@@ -209,7 +209,7 @@ class PyosysStep(Step):
         Variable(
             "SYNTH_CORNER",
             Optional[str],
-            "IPVT corners to use during resizer optimizations. If unspecified, the value for `STA_CORNERS` from the PDK will be used.",
+            "A fully qualified IPVT corner to use during synthesis. If unspecified, the value for `DEFAULT_CORNER` from the PDK will be used.",
             pdk=True,
         ),
     ]
@@ -249,6 +249,8 @@ def get_command(self, state_in: State) -> List[str]:
         scl_lib_list = self.toolbox.filter_views(
             self.config, self.config["LIB"], self.config.get("SYNTH_CORNER")
         )
+        print(scl_lib_list)
+        exit()
         if self.power_defines and self.config["CELL_VERILOG_MODELS"] is not None:
             blackbox_models.extend(
                 [

diff --git a/pyproject.toml b/pyproject.toml
@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "openlane"
-version = "3.0.0.dev5"
+version = "3.0.0.dev6"
 description = "An infrastructure for implementing chip design flows"
 authors = ["Efabless Corporation and Contributors <donn@efabless.com>"]
 readme = "Readme.md"