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* updated stuff * +update * + module tests * +module tests * serializer update and more * merged into branch+ * updated hdl-parser tests * + vhdl_parser tests * commented out failed test * renamed insert_gate/insert_net to assign_gate/assign_net after merge * + parser test * copied old hdl-writer tests * included hdl-writer/ * +parser/writer tests * updated tests after some changes * started verilog parser tests * +verilog parser tests * added .v parser tests + removed wrong TODOs * +verilog parser tests * +first numeric literal tests * allow empty value and datatype * updated datacontainer test
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