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@swallat swallat released this 27 Jun 10:34
· 5130 commits to master since this release
v1.1.0
d85490f
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Learn about vigilant mode.
  • Added Support for Xilinx Unisim gate library
  • Added Support for Xilinx Simprim gate library
  • Added Support for Synopsys 90nm gate library
  • Added Support for GSCLIB 3.0 gate library
  • Added Support for UMC 0.18 um gate library
  • Added VHDL and Verilog parser fixes
  • Fixeds issue #143
  • Fixed static lint issues
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