Merge branch 'devel'

hdl/modules/bpm_cores_pkg.vhd

@@ -478,6 +478,7 @@ package bpm_cores_pkg is
 
       -- Swap frequency settings
       swap_div_f_i      : in  std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
+      swap_div_f_cnt_en_i : in  std_logic := '1';
 
       -- De-swap delay setting
       deswap_delay_i    : in  std_logic_vector(g_delay_vec_width-1 downto 0)
@@ -834,6 +835,11 @@ package bpm_cores_pkg is
 
         sync_trig_slow_i  : in std_logic;
 
+        -----------------------------
+        -- Trigger for resetting counters (all rates)
+        -----------------------------
+        sync_counters_i   : in std_logic;
+
         -----------------------------
         -- Debug signals
         -----------------------------
@@ -1072,6 +1078,11 @@ package bpm_cores_pkg is
 
         sync_trig_slow_i  : in std_logic;
 
+        -----------------------------
+        -- Trigger for resetting counters (all rates)
+        -----------------------------
+        sync_counters_i   : in std_logic;
+
         -----------------------------
         -- Debug signals
         -----------------------------

hdl/modules/wb_bpm_swap/bpm_swap/bpm_swap.vhd

@@ -53,6 +53,7 @@ entity bpm_swap is
 
     -- Swap frequency settings
     swap_div_f_i      : in  std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
+    swap_div_f_cnt_en_i : in  std_logic := '1';
 
     -- De-swap delay setting
     deswap_delay_i    : in  std_logic_vector(g_delay_vec_width-1 downto 0)
@@ -123,6 +124,7 @@ begin
     rst_n_i            =>  rst_n_i,
     sync_trig_i        =>  sync_trig_i,
     swap_mode_i        =>  swap_mode_i,
+    swap_div_f_cnt_en_i => swap_div_f_cnt_en_i,
     swap_div_f_i       =>  swap_div_f_i,
     deswap_delay_i     =>  deswap_delay_i,
     swap_o             =>  swap,

hdl/modules/wb_bpm_swap/wb_bpm_swap.vhd

@@ -210,6 +210,7 @@ begin
     rffe_swclk_o                            =>  rffe_swclk_o,
     sync_trig_i                             =>  sync_trig_i,
     swap_mode_i                             =>  regs_out.ctrl_mode_o,
+    swap_div_f_cnt_en_i                     =>  regs_out.ctrl_swap_div_f_cnt_en_o,
     swap_div_f_i                            =>  regs_out.ctrl_swap_div_f_o,
     deswap_delay_i                          =>  deswap_delay
   );

hdl/modules/wb_bpm_swap/wbgen/doc/wb_bpm_swap_regs_wb.html

@@ -98,7 +98,7 @@ <h3><a name="sect_2_0">2. HDL symbol</a></h3>
 &rarr;
 </td>
 <td  class="td_pblock_left">
-rst_n_i
+wb_adr_i
 </td>
 <td  class="td_sym_center">
 
@@ -112,10 +112,10 @@ <h3><a name="sect_2_0">2. HDL symbol</a></h3>
 </tr>
 <tr>
 <td  class="td_arrow_left">
-&rarr;
+&rArr;
 </td>
 <td  class="td_pblock_left">
-clk_sys_i
+wb_dat_i[31:0]
 </td>
 <td  class="td_sym_center">
 
@@ -129,10 +129,10 @@ <h3><a name="sect_2_0">2. HDL symbol</a></h3>
 </tr>
 <tr>
 <td  class="td_arrow_left">
-&rarr;
+&lArr;
 </td>
 <td  class="td_pblock_left">
-wb_adr_i
+wb_dat_o[31:0]
 </td>
 <td  class="td_sym_center">
 
@@ -146,10 +146,10 @@ <h3><a name="sect_2_0">2. HDL symbol</a></h3>
 </tr>
 <tr>
 <td  class="td_arrow_left">
-&rArr;
+&rarr;
 </td>
 <td  class="td_pblock_left">
-wb_dat_i[31:0]
+wb_cyc_i
 </td>
 <td  class="td_sym_center">
 
@@ -163,104 +163,104 @@ <h3><a name="sect_2_0">2. HDL symbol</a></h3>
 </tr>
 <tr>
 <td  class="td_arrow_left">
-&lArr;
+&rArr;
 </td>
 <td  class="td_pblock_left">
-wb_dat_o[31:0]
+wb_sel_i[3:0]
 </td>
 <td  class="td_sym_center">
 
 </td>
 <td  class="td_pblock_right">
-bpm_swap_ctrl_swap_div_f_o[15:0]
+bpm_swap_ctrl_swap_div_f_cnt_en_o
 </td>
 <td  class="td_arrow_right">
-&rArr;
+&rarr;
 </td>
 </tr>
 <tr>
 <td  class="td_arrow_left">
 &rarr;
 </td>
 <td  class="td_pblock_left">
-wb_cyc_i
+wb_stb_i
 </td>
 <td  class="td_sym_center">
-&nbsp;
+
 </td>
 <td  class="td_pblock_right">
-
+bpm_swap_ctrl_swap_div_f_o[15:0]
 </td>
 <td  class="td_arrow_right">
-
+&rArr;
 </td>
 </tr>
 <tr>
 <td  class="td_arrow_left">
-&rArr;
+&rarr;
 </td>
 <td  class="td_pblock_left">
-wb_sel_i[3:0]
+wb_we_i
 </td>
 <td  class="td_sym_center">
-
+&nbsp;
 </td>
 <td  class="td_pblock_right">
-<b>Delay:</b>
+
 </td>
 <td  class="td_arrow_right">
 
 </td>
 </tr>
 <tr>
 <td  class="td_arrow_left">
-&rarr;
+&larr;
 </td>
 <td  class="td_pblock_left">
-wb_stb_i
+wb_ack_o
 </td>
 <td  class="td_sym_center">
 
 </td>
 <td  class="td_pblock_right">
-bpm_swap_dly_deswap_o[15:0]
+<b>Delay:</b>
 </td>
 <td  class="td_arrow_right">
-&rArr;
+
 </td>
 </tr>
 <tr>
 <td  class="td_arrow_left">
-&rarr;
+&larr;
 </td>
 <td  class="td_pblock_left">
-wb_we_i
+wb_err_o
 </td>
 <td  class="td_sym_center">
 
 </td>
 <td  class="td_pblock_right">
-bpm_swap_dly_reserved_i[15:0]
+bpm_swap_dly_deswap_o[15:0]
 </td>
 <td  class="td_arrow_right">
-&lArr;
+&rArr;
 </td>
 </tr>
 <tr>
 <td  class="td_arrow_left">
 &larr;
 </td>
 <td  class="td_pblock_left">
-wb_ack_o
+wb_rty_o
 </td>
 <td  class="td_sym_center">
 
 </td>
 <td  class="td_pblock_right">
-
+bpm_swap_dly_reserved_i[15:0]
 </td>
 <td  class="td_arrow_right">
-
+&lArr;
 </td>
 </tr>
 <tr>
@@ -518,8 +518,8 @@ <h3><a name="sect_3_1">3.1. Control Signals</a></h3>
 <td  class="td_unused">
 -
 </td>
-<td  class="td_unused">
--
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+SWAP_DIV_F_CNT_EN
 </td>
 <td style="border: solid 1px black;" colspan=2  class="td_field">
 RESERVED[1:0]
@@ -552,6 +552,10 @@ <h3><a name="sect_3_1">3.1. Control Signals</a></h3>
 </b>[<i>read-only</i>]: Reserved
 <br>Ignore on write, read as 0's
 <li><b>
+SWAP_DIV_F_CNT_EN
+</b>[<i>read/write</i>]: Enable Swap Phase Syncing
+<br>Enables swap phase syncing
+<li><b>
 SWAP_DIV_F
 </b>[<i>read/write</i>]: Swap Divisor
 <br>Divider of clock input

hdl/modules/wb_bpm_swap/wbgen/wb_bpm_swap.wb

@@ -13,6 +13,7 @@
 -- Revisions  :
 -- Date        Version  Author                Description
 -- 2013-04-10  1.0      jose.berkenbrock      Created
+-- 2023-07-13  1.1      guilherme.ricioli     Add swap_div_f_cnt_en field
 -------------------------------------------------------------------------------
 
 peripheral {
@@ -59,6 +60,15 @@ peripheral {
        access_dev = WRITE_ONLY;
     };
 
+    field {
+       name = "Enable Swap Phase Syncing";
+       description = "Enables swap phase syncing";
+       prefix = "swap_div_f_cnt_en";
+       type = BIT;
+       access_bus = READ_WRITE;
+       access_dev = READ_ONLY;
+    };
+
     field {
        name = "Swap Divisor";
        description = "Divider of clock input";

hdl/modules/wb_bpm_swap/wbgen/wb_bpm_swap_regs.h

@@ -3,7 +3,7 @@
 
   * File           : wb_bpm_swap_regs.h
   * Author         : auto-generated by wbgen2 from wb_bpm_swap.wb
-  * Created        : Thu Jul 20 14:33:08 2017
+  * Created        : Thu Jul 13 16:52:28 2023
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_bpm_swap.wb
@@ -14,7 +14,11 @@
 #ifndef __WBGEN2_REGDEFS_WB_BPM_SWAP_WB
 #define __WBGEN2_REGDEFS_WB_BPM_SWAP_WB
 
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
 #include <inttypes.h>
+#endif
 
 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))
@@ -48,6 +52,9 @@
 #define BPM_SWAP_CTRL_RESERVED_W(value)       WBGEN2_GEN_WRITE(value, 3, 2)
 #define BPM_SWAP_CTRL_RESERVED_R(reg)         WBGEN2_GEN_READ(reg, 3, 2)
 
+/* definitions for field: Enable Swap Phase Syncing in reg: Control Signals */
+#define BPM_SWAP_CTRL_SWAP_DIV_F_CNT_EN       WBGEN2_GEN_MASK(5, 1)
+
 /* definitions for field: Swap Divisor in reg: Control Signals */
 #define BPM_SWAP_CTRL_SWAP_DIV_F_MASK         WBGEN2_GEN_MASK(8, 16)
 #define BPM_SWAP_CTRL_SWAP_DIV_F_SHIFT        8

hdl/modules/wb_bpm_swap/wbgen/wb_bpm_swap_regs.vhd

@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wb_bpm_swap_regs.vhd
 -- Author         : auto-generated by wbgen2 from wb_bpm_swap.wb
--- Created        : Thu Jul 20 14:33:08 2017
+-- Created        : Thu Jul 13 16:52:28 2023
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_bpm_swap.wb
@@ -29,6 +29,8 @@ entity wb_bpm_swap_regs is
     wb_stb_i                                 : in     std_logic;
     wb_we_i                                  : in     std_logic;
     wb_ack_o                                 : out    std_logic;
+    wb_err_o                                 : out    std_logic;
+    wb_rty_o                                 : out    std_logic;
     wb_stall_o                               : out    std_logic;
     fs_clk_i                                 : in     std_logic;
     regs_i                                   : in     t_bpm_swap_in_registers;
@@ -45,6 +47,7 @@ signal bpm_swap_ctrl_mode_swb_delay             : std_logic      ;
 signal bpm_swap_ctrl_mode_swb_s0                : std_logic      ;
 signal bpm_swap_ctrl_mode_swb_s1                : std_logic      ;
 signal bpm_swap_ctrl_mode_swb_s2                : std_logic      ;
+signal bpm_swap_ctrl_swap_div_f_cnt_en_int      : std_logic      ;
 signal bpm_swap_ctrl_swap_div_f_int             : std_logic_vector(15 downto 0);
 signal bpm_swap_ctrl_swap_div_f_swb             : std_logic      ;
 signal bpm_swap_ctrl_swap_div_f_swb_delay       : std_logic      ;
@@ -69,13 +72,8 @@ signal allones                                  : std_logic_vector(31 downto 0);
 signal allzeros                                 : std_logic_vector(31 downto 0);
 
 begin
--- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
   wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
   process (clk_sys_i, rst_n_i)
@@ -88,6 +86,7 @@ begin
       bpm_swap_ctrl_mode_int <= "00";
       bpm_swap_ctrl_mode_swb <= '0';
       bpm_swap_ctrl_mode_swb_delay <= '0';
+      bpm_swap_ctrl_swap_div_f_cnt_en_int <= '0';
       bpm_swap_ctrl_swap_div_f_int <= "0000000000000000";
       bpm_swap_ctrl_swap_div_f_swb <= '0';
       bpm_swap_ctrl_swap_div_f_swb_delay <= '0';
@@ -118,15 +117,16 @@ begin
               bpm_swap_ctrl_mode_int <= wrdata_reg(2 downto 1);
               bpm_swap_ctrl_mode_swb <= '1';
               bpm_swap_ctrl_mode_swb_delay <= '1';
+              bpm_swap_ctrl_swap_div_f_cnt_en_int <= wrdata_reg(5);
               bpm_swap_ctrl_swap_div_f_int <= wrdata_reg(23 downto 8);
               bpm_swap_ctrl_swap_div_f_swb <= '1';
               bpm_swap_ctrl_swap_div_f_swb_delay <= '1';
             end if;
             rddata_reg(0) <= bpm_swap_ctrl_rst_int;
             rddata_reg(2 downto 1) <= bpm_swap_ctrl_mode_int;
             rddata_reg(4 downto 3) <= regs_i.ctrl_reserved_i;
+            rddata_reg(5) <= bpm_swap_ctrl_swap_div_f_cnt_en_int;
             rddata_reg(23 downto 8) <= bpm_swap_ctrl_swap_div_f_int;
-            rddata_reg(5) <= 'X';
             rddata_reg(6) <= 'X';
             rddata_reg(7) <= 'X';
             rddata_reg(24) <= 'X';
@@ -185,6 +185,8 @@ begin
 
 
 -- Reserved
+-- Enable Swap Phase Syncing
+  regs_o.ctrl_swap_div_f_cnt_en_o <= bpm_swap_ctrl_swap_div_f_cnt_en_int;
 -- Swap Divisor
 -- asynchronous std_logic_vector register : Swap Divisor (type RW/RO, fs_clk_i <-> clk_sys_i)
   process (fs_clk_i, rst_n_i)
@@ -228,6 +230,8 @@ begin
 -- Reserved
   rwaddr_reg <= wb_adr_i;
   wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+  wb_err_o <= '0';
+  wb_rty_o <= '0';
 -- ACK signal generation. Just pass the LSB of ACK counter.
   wb_ack_o <= ack_sreg(0);
 end syn;