Matthew Allen and Andrew Bakhit's ECE 425L Design Cal Poly Pomona | Spring 2015 | Dr. Halima el Naga
To design, build and implement a pipelined MIPS processor on an FPGA for a lab course.
Lab 1: Verilog Recap; Mux and Decoder; 2's complement adder/subtractor; shift register Lab 2: ALU Lab 3: Register File and Data File Lab 4: Single-Cycle MCU; Datapath and Control Lab 5: 5-Stage Pipelined MCU