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1. CPU_HW_Design CPU_HW_Design Public

   single-cycle and pipelined CPU designs, with a focus on ARM and MIPS instruction sets with/without Cache

   Verilog

2. DLD_CAs DLD_CAs Public

   Digital Logic Design (ECE 367) - Spring 1399-00 - University of Tehran

   Verilog

3. DS_Fall2022_CAs DS_Fall2022_CAs Public

   Data Structure course by Dr. Feili & Faghih @ University of Tehran, Fall 2022

   Python