Update pulp_riscv_dbg to pulp-platform/riscv-dbg@358f901

Update code from upstream repository https://github.com/pulp- platform/riscv-dbg to revision 358f90110220adf7a083f8b65d157e836d706236 This also connects the nextdm input and ndmreset ack inputs in rv_dm, and ties them off. Implementation of ndmreset ack comes in a subsequent commit. Fixes lowRISC#19750 Signed-off-by: Michael Schaffner <msf@opentitan.org>
msfschaffner · Mar 15, 2024 · 08b6c28 · 08b6c28
1 parent a72c869
commit 08b6c28
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Showing 22 changed files with 406 additions and 53 deletions.
diff --git a/hw/ip/lc_ctrl/rtl/lc_ctrl.sv b/hw/ip/lc_ctrl/rtl/lc_ctrl.sv
@@ -212,7 +212,8 @@ module lc_ctrl
   logic req_ready;
   assign req_ready = dmi_req_ready & dmi_resp_ready;
   dmi_jtag #(
-    .IdcodeValue(IdcodeValue)
+    .IdcodeValue(IdcodeValue),
+    .NumDmiWordAbits(7)
   ) u_dmi_jtag (
     .clk_i,
     .rst_ni,
@@ -264,6 +265,7 @@ module lc_ctrl
   // These signals are unused
   logic unused_tap_tl_d2h;
   assign unused_tap_tl_d2h = ^{
+    dmi_req.addr[31:30],
     tap_tl_d2h.d_opcode,
     tap_tl_d2h.d_param,
     tap_tl_d2h.d_size,

diff --git a/hw/ip/rv_dm/data/rv_dm.hjson b/hw/ip/rv_dm/data/rv_dm.hjson
@@ -55,6 +55,18 @@
     }
   ],
   inter_signal_list: [
+    {
+      package: "rv_dm_pkg"
+      struct:  "next_dm_addr"
+      type:    "uni"
+      name:    "next_dm_addr"
+      act:     "rcv"
+      default: "'0"
+      desc:    '''
+               32bit word address of the next debug module.
+               Set to 0x0 if this is the last debug module in the chain.
+               '''
+    },
     { struct:  "jtag",
       type:    "req_rsp",
       name:    "jtag",

diff --git a/hw/ip/rv_dm/doc/interfaces.md b/hw/ip/rv_dm/doc/interfaces.md
@@ -17,6 +17,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
 
 | Port Name                | Package::Struct                    | Type    | Act   |   Width | Description                                                                                                                                                                                                                                                                         |
 |:-------------------------|:-----------------------------------|:--------|:------|--------:|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
+| next_dm_addr             | rv_dm_pkg::next_dm_addr            | uni     | rcv   |       1 | 32bit word address of the next debug module. Set to 0x0 if this is the last debug module in the chain.                                                                                                                                                                              |
 | jtag                     | jtag_pkg::jtag                     | req_rsp | rsp   |       1 | JTAG signals for the RISC-V TAP.                                                                                                                                                                                                                                                    |
 | lc_hw_debug_en           | lc_ctrl_pkg::lc_tx                 | uni     | rcv   |       1 | Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the hardware debug mechanisms are enabled in the system.                                                                                                                          |
 | lc_dft_en                | lc_ctrl_pkg::lc_tx                 | uni     | rcv   |       1 | Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the DFT mechanisms are enabled in the system.                                                                                                                                     |

diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv
@@ -21,6 +21,7 @@ module rv_dm
   input  logic                clk_i,       // clock
   input  logic                rst_ni,      // asynchronous reset active low, connect PoR
                                            // here, not the system reset
+  input  logic [31:0]         next_dm_addr_i, // static word address of the next debug module.
   // SEC_CM: LC_HW_DEBUG_EN.INTERSIG.MUBI
   // HW Debug lifecycle enable signal (live version from the life cycle controller)
   input  lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i,
@@ -402,7 +403,8 @@ module rv_dm
 
   // JTAG TAP
   dmi_jtag #(
-    .IdcodeValue    (IdcodeValue)
+    .IdcodeValue    (IdcodeValue),
+    .NumDmiWordAbits(7)
   ) dap (
     .clk_i            (clk_i),
     .rst_ni           (rst_ni),
@@ -497,8 +499,10 @@ module rv_dm
   ) u_dm_top (
     .clk_i,
     .rst_ni,
+    .next_dm_addr_i,
     .testmode_i            (testmode              ),
     .ndmreset_o            (ndmreset_req          ),
+    .ndmreset_ack_i        (ndmreset_req          ),
     .dmactive_o,
     .debug_req_o           (debug_req             ),
     .unavailable_i,

diff --git a/hw/ip/rv_dm/rtl/rv_dm_pkg.sv b/hw/ip/rv_dm/rtl/rv_dm_pkg.sv
@@ -0,0 +1,12 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+
+package rv_dm_pkg;
+
+  typedef logic [31:0] next_dm_addr_t;
+
+  parameter next_dm_addr_t NEXT_DM_ADDR_DEFAULT = '0;
+
+endpackage : rv_dm_pkg
diff --git a/hw/ip/rv_dm/rv_dm.core b/hw/ip/rv_dm/rv_dm.core
@@ -20,6 +20,7 @@ filesets:
     files:
       - rtl/rv_dm_reg_pkg.sv
       - rtl/rv_dm_regs_reg_top.sv
+      - rtl/rv_dm_pkg.sv
       - rtl/rv_dm.sv
     file_type: systemVerilogSource
 

diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -5207,6 +5207,22 @@
       ]
       inter_signal_list:
       [
+        {
+          name: next_dm_addr
+          desc:
+            '''
+            32bit word address of the next debug module.
+            Set to 0x0 if this is the last debug module in the chain.
+            '''
+          struct: next_dm_addr
+          package: rv_dm_pkg
+          type: uni
+          act: rcv
+          width: 1
+          default: "'0"
+          inst_name: rv_dm
+          index: -1
+        }
         {
           name: jtag
           desc: JTAG signals for the RISC-V TAP.
@@ -18670,6 +18686,22 @@
         top_signame: flash_ctrl_mem_tl
         index: -1
       }
+      {
+        name: next_dm_addr
+        desc:
+          '''
+          32bit word address of the next debug module.
+          Set to 0x0 if this is the last debug module in the chain.
+          '''
+        struct: next_dm_addr
+        package: rv_dm_pkg
+        type: uni
+        act: rcv
+        width: 1
+        default: "'0"
+        inst_name: rv_dm
+        index: -1
+      }
       {
         name: jtag
         desc: JTAG signals for the RISC-V TAP.

diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -2153,6 +2153,7 @@ module top_earlgrey #(
       .alert_rx_i  ( alert_rx[40:40] ),
 
       // Inter-module signals
+      .next_dm_addr_i('0),
       .jtag_i(pinmux_aon_rv_jtag_req),
       .jtag_o(pinmux_aon_rv_jtag_rsp),
       .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),

diff --git a/hw/vendor/patches/pulp_riscv_dbg/0001-Fix-lint-errors.patch b/hw/vendor/patches/pulp_riscv_dbg/0001-Fix-lint-errors.patch
@@ -1,15 +1,32 @@
-From e0f9a11ece9c212d5d59183cb4263af415e0ea23 Mon Sep 17 00:00:00 2001
+From 144819373e52cbc15ecb19cf11b374be41a26016 Mon Sep 17 00:00:00 2001
 From: Michael Schaffner <msf@google.com>
 Date: Tue, 25 Oct 2022 18:28:07 -0700
-Subject: [PATCH 1/3] Fix lint errors
+Subject: [PATCH 1/7] Fix lint errors
 
 Signed-off-by: Michael Schaffner <msf@google.com>
 
 diff --git a/src/dm_mem.sv b/src/dm_mem.sv
-index b14b390..5b2c556 100755
+index 9ff3c86..62cdf02 100755
 --- a/src/dm_mem.sv
 +++ b/src/dm_mem.sv
-@@ -265,12 +265,13 @@ module dm_mem #(
+@@ -82,7 +82,15 @@ module dm_mem #(
+   localparam logic [DbgAddressBits-1:0] ResumingAddr  = 'h110;
+   localparam logic [DbgAddressBits-1:0] ExceptionAddr = 'h118;
+
+-  logic [dm::ProgBufSize/2-1:0][63:0]   progbuf;
++  localparam logic [DbgAddressBits-1:0] RomBaseAddr   = dm::HaltAddress;
++  // The size is arbitrarily set to 0x800, so as to make the dm_space exactly 0x900 long. This is
++  // more than eough to cover the 19 x 64bit = 0x98 bytes currenty allocated in the debug ROM.
++  localparam logic [DbgAddressBits-1:0] RomEndAddr    = dm::HaltAddress + 'h7FF;
++  // Prog buff size after repacking the 32bit array into a 64bit array.
++  localparam int unsigned ProgBuf64Size = dm::ProgBufSize / 2;
++  localparam int unsigned ProgBuf64AddrSize = $clog2(ProgBuf64Size);
++
++  logic [ProgBuf64Size-1:0][63:0] progbuf;
+   logic [7:0][63:0]   abstract_cmd;
+   logic [NrHarts-1:0] halted_d, halted_q;
+   logic [NrHarts-1:0] resuming_d, resuming_q;
+@@ -265,12 +273,13 @@ module dm_mem #(
            // core can write data registers
            [DataBaseAddr:DataEndAddr]: begin
              data_valid_o = 1'b1;
@@ -26,7 +43,7 @@ index b14b390..5b2c556 100755
                          data_bits[dc+1][(i-4)*8+:8] = wdata_i[i*8+:8];
                        end
                      end else begin // for lower 32bit data write
-@@ -310,8 +311,11 @@ module dm_mem #(
+@@ -310,14 +319,17 @@ module dm_mem #(
 
            [DataBaseAddr:DataEndAddr]: begin
              rdata_d = {
@@ -40,8 +57,16 @@ index b14b390..5b2c556 100755
                        };
            end
 
+           [ProgBufBaseAddr:ProgBufEndAddr]: begin
+-            rdata_d = progbuf[$clog2(dm::ProgBufSize)'(addr_i[DbgAddressBits-1:3] -
+-                          ProgBufBaseAddr[DbgAddressBits-1:3])];
++            rdata_d = progbuf[ProgBuf64AddrSize'(addr_i[DbgAddressBits-1:3] -
++                                                 ProgBufBaseAddr[DbgAddressBits-1:3])];
+           end
+
+           // two slots for abstract command
 diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
-index e897bf5..6be89a6 100644
+index 577c3fd..24edad0 100644
 --- a/src/dmi_jtag.sv
 +++ b/src/dmi_jtag.sv
 @@ -58,6 +58,7 @@ module dmi_jtag #(

diff --git a/hw/vendor/patches/pulp_riscv_dbg/0002-Add-access-error-signal-to-dm_mem.patch b/hw/vendor/patches/pulp_riscv_dbg/0002-Add-access-error-signal-to-dm_mem.patch
@@ -1,12 +1,12 @@
-From 107fe81668549a470caccc46aad1d74c1647042c Mon Sep 17 00:00:00 2001
+From d2fe1d8aa26b8d6c03ada39962bdf779d0c43efd Mon Sep 17 00:00:00 2001
 From: Michael Schaffner <msf@google.com>
 Date: Tue, 25 Oct 2022 19:38:49 -0700
-Subject: [PATCH 2/3] Add access error signal to dm_mem
+Subject: [PATCH 2/7] Add access error signal to dm_mem
 
 Signed-off-by: Michael Schaffner <msf@google.com>
 
 diff --git a/src/dm_mem.sv b/src/dm_mem.sv
-index 5b2c556..cc0cc69 100755
+index 62cdf02..f7a5f7d 100755
 --- a/src/dm_mem.sv
 +++ b/src/dm_mem.sv
 @@ -20,7 +20,8 @@ module dm_mem #(
@@ -31,27 +31,15 @@ index 5b2c556..cc0cc69 100755
  );
    localparam int unsigned DbgAddressBits = 12;
    localparam int unsigned HartSelLen     = (NrHarts == 1) ? 1 : $clog2(NrHarts);
-@@ -82,6 +84,11 @@ module dm_mem #(
-   localparam logic [DbgAddressBits-1:0] ResumingAddr  = 'h110;
-   localparam logic [DbgAddressBits-1:0] ExceptionAddr = 'h118;
-
-+  localparam logic [DbgAddressBits-1:0] RomBaseAddr   = dm::HaltAddress;
-+  // The size is arbitrarily set to 0x800, so as to make the dm_space exactly 0x900 long. This is
-+  // more than eough to cover the 19 x 64bit = 0x98 bytes currenty allocated in the debug ROM.
-+  localparam logic [DbgAddressBits-1:0] RomEndAddr    = dm::HaltAddress + 'h7FF;
-+
-   logic [dm::ProgBufSize/2-1:0][63:0]   progbuf;
-   logic [7:0][63:0]   abstract_cmd;
-   logic [NrHarts-1:0] halted_d, halted_q;
-@@ -231,6 +238,7 @@ module dm_mem #(
+@@ -239,6 +241,7 @@ module dm_mem #(
      rdata_d        = rdata_q;
      data_bits      = data_i;
      rdata          = '0;
 +    fwd_rom_d      = 1'b0;
 
      // write data in csr register
      data_valid_o   = 1'b0;
-@@ -282,7 +290,7 @@ module dm_mem #(
+@@ -290,7 +293,7 @@ module dm_mem #(
                end
              end
            end
@@ -60,7 +48,7 @@ index 5b2c556..cc0cc69 100755
          endcase
 
        // this is a read
-@@ -339,6 +347,11 @@ module dm_mem #(
+@@ -347,6 +350,11 @@ module dm_mem #(
              end
              rdata_d = rdata;
            end
@@ -72,7 +60,7 @@ index 5b2c556..cc0cc69 100755
            default: ;
          endcase
        end
-@@ -353,6 +366,54 @@ module dm_mem #(
+@@ -361,6 +369,54 @@ module dm_mem #(
      data_o = data_bits;
    end
 
@@ -127,7 +115,7 @@ index 5b2c556..cc0cc69 100755
    always_comb begin : p_abstract_cmd_rom
      // this abstract command is currently unsupported
      unsupported_command = 1'b0;
-@@ -517,10 +578,6 @@ module dm_mem #(
+@@ -527,10 +583,6 @@ module dm_mem #(
      );
    end
 

diff --git a/hw/vendor/patches/pulp_riscv_dbg/0003-Use-lowrisc-instead-of-PULP-primitives.patch b/hw/vendor/patches/pulp_riscv_dbg/0003-Use-lowrisc-instead-of-PULP-primitives.patch
@@ -1,7 +1,7 @@
-From 51db2dfa1d52ea995f244fba457a101215381382 Mon Sep 17 00:00:00 2001
+From 9323ea206e15381283e67a780aac8ffbb5a5d19b Mon Sep 17 00:00:00 2001
 From: Michael Schaffner <msf@google.com>
 Date: Tue, 25 Oct 2022 18:27:27 -0700
-Subject: [PATCH 3/3] Use lowrisc instead of PULP primitives
+Subject: [PATCH 3/7] Use lowrisc instead of PULP primitives
 
 Signed-off-by: Michael Schaffner <msf@google.com>
 
@@ -235,7 +235,7 @@ index f9d66fd..ef9e57c 100644
 
  endmodule : dmi_cdc
 diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv
-index 6be89a6..a7e5bff 100644
+index 24edad0..f8b8483 100644
 --- a/src/dmi_jtag.sv
 +++ b/src/dmi_jtag.sv
 @@ -22,9 +22,10 @@ module dmi_jtag #(