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Update pulp_riscv_dbg to pulp-platform/riscv-dbg@358f901
Update code from upstream repository https://github.com/pulp- platform/riscv-dbg to revision 358f90110220adf7a083f8b65d157e836d706236 This also connects the nextdm input and ndmreset ack inputs in rv_dm, and ties them off. Implementation of ndmreset ack comes in a subsequent commit. Fixes lowRISC#19750 Signed-off-by: Michael Schaffner <msf@opentitan.org>
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,12 @@ | ||
| // Copyright lowRISC contributors. | ||
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
| // | ||
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| package rv_dm_pkg; | ||
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| typedef logic [31:0] next_dm_addr_t; | ||
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| parameter next_dm_addr_t NEXT_DM_ADDR_DEFAULT = '0; | ||
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| endpackage : rv_dm_pkg |
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95 changes: 95 additions & 0 deletions
95
hw/vendor/patches/pulp_riscv_dbg/0004-Extend-DMI-address-width.patch
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,95 @@ | ||
| From 4dba770c0a4944c1288ed80e0a4289a1e19e77c8 Mon Sep 17 00:00:00 2001 | ||
| From: Michael Schaffner <msf@opentitan.org> | ||
| Date: Thu, 17 Aug 2023 10:30:17 -0700 | ||
| Subject: [PATCH 4/7] Extend DMI address width | ||
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| Make the DMI interface address 32bits so that larger | ||
| address ranges can be supported (e.g. to take advantage | ||
| of a TL-UL to DMI bridge). | ||
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| The effective number of address bits is made configurable | ||
| in the TAP so that this can be determined based on | ||
| the specific integration. | ||
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| Signed-off-by: Michael Schaffner <msf@opentitan.org> | ||
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| diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv | ||
| index 259f3fc..b899b17 100644 | ||
| --- a/src/dm_csrs.sv | ||
| +++ b/src/dm_csrs.sv | ||
| @@ -87,7 +87,6 @@ module dm_csrs #( | ||
| dm::dtm_op_e dtm_op; | ||
| assign dtm_op = dm::dtm_op_e'(dmi_req_i.op); | ||
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| - | ||
| localparam dm::dm_csr_e DataEnd = dm::dm_csr_e'(dm::Data0 + {4'h0, dm::DataCount} - 8'h1); | ||
| localparam dm::dm_csr_e ProgBufEnd = dm::dm_csr_e'(dm::ProgBuf0 + {4'h0, dm::ProgBufSize} - 8'h1); | ||
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| @@ -212,6 +211,9 @@ module dm_csrs #( | ||
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| // Get the data index, i.e. 0 for dm::Data0 up to 11 for dm::Data11 | ||
| assign dm_csr_addr = dm::dm_csr_e'({1'b0, dmi_req_i.addr}); | ||
| + logic unused_addr_bits; | ||
| + assign unused_addr_bits = ^dmi_req_i.addr[31:$bits(dm_csr_addr)]; | ||
| + | ||
| // Xilinx Vivado 2020.1 does not allow subtraction of two enums; do the subtraction with logic | ||
| // types instead. | ||
| assign autoexecdata_idx = 4'({dm_csr_addr} - {dm::Data0}); | ||
| diff --git a/src/dm_pkg.sv b/src/dm_pkg.sv | ||
| index cc2e1eb..a8a27d2 100644 | ||
| --- a/src/dm_pkg.sv | ||
| +++ b/src/dm_pkg.sv | ||
| @@ -222,7 +222,7 @@ package dm; | ||
| } sbcs_t; | ||
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| typedef struct packed { | ||
| - logic [6:0] addr; | ||
| + logic [31:0] addr; | ||
| dtm_op_e op; | ||
| logic [31:0] data; | ||
| } dmi_req_t; | ||
| diff --git a/src/dmi_jtag.sv b/src/dmi_jtag.sv | ||
| index f8b8483..a467292 100644 | ||
| --- a/src/dmi_jtag.sv | ||
| +++ b/src/dmi_jtag.sv | ||
| @@ -18,6 +18,7 @@ | ||
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| module dmi_jtag #( | ||
| parameter logic [31:0] IdcodeValue = 32'h00000DB3 | ||
| + parameter int unsigned NumDmiWordAbits = 16 // Number of DMI address bits (7 - 32) | ||
| ) ( | ||
| input logic clk_i, // DMI Clock | ||
| input logic rst_ni, // Asynchronous reset active low | ||
| @@ -78,7 +79,7 @@ module dmi_jtag #( | ||
| zero0 : '0, | ||
| idle : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately | ||
| dmistat : error_q, // 0: No error, 2: Op failed, 3: too fast | ||
| - abits : 6'd7, // The size of address in dmi | ||
| + abits : 6'(NumDmiWordAbits), // The size of address in dmi | ||
| version : 4'd1 // Version described in spec version 0.13 (and later?) | ||
| }; | ||
| end | ||
| @@ -113,7 +114,7 @@ module dmi_jtag #( | ||
| logic dmi_resp_ready; | ||
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| typedef struct packed { | ||
| - logic [6:0] address; | ||
| + logic [NumDmiWordAbits-1:0] address; | ||
| logic [31:0] data; | ||
| logic [1:0] op; | ||
| } dmi_t; | ||
| @@ -122,12 +123,12 @@ module dmi_jtag #( | ||
| state_e state_d, state_q; | ||
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| logic [$bits(dmi_t)-1:0] dr_d, dr_q; | ||
| - logic [6:0] address_d, address_q; | ||
| + logic [NumDmiWordAbits-1:0] address_d, address_q; | ||
| logic [31:0] data_d, data_q; | ||
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| dmi_t dmi; | ||
| assign dmi = dmi_t'(dr_q); | ||
| - assign dmi_req.addr = address_q; | ||
| + assign dmi_req.addr = $bits(dmi_req.addr)'(address_q); | ||
| assign dmi_req.data = data_q; | ||
| assign dmi_req.op = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ; | ||
| // We will always be ready to accept the data we requested. |
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