hal/ia32: Add support for Local APIC timer

- Move code reading and writing to Local APIC to its own functions. - Add detection of Local APIC Timer's frequency. - Make Local APIC timer the default timer for scheduling JIRA: RTOS-530
phoenix-rtos · Nov 8, 2023 · 086a5b9 · 086a5b9
1 parent 7b8d68b
commit 086a5b9
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Showing 6 changed files with 274 additions and 54 deletions.
diff --git a/hal/ia32/arch/interrupts.h b/hal/ia32/arch/interrupts.h
@@ -34,6 +34,8 @@
 #define IOAPIC_INTPOL   (1u << 13)
 #define IOAPIC_DESTMOD  (1u << 11)
 
+#define LAPIC_EOI 0
+
 /* Interrupt source override polarity flags */
 #define MADT_ISO_POLAR_MASK 0x3
 #define MADT_ISO_POLAR_BUS  0x0

diff --git a/hal/ia32/cpu.c b/hal/ia32/cpu.c
@@ -27,6 +27,8 @@
 #include "tlb.h"
 #include "init.h"
 
+extern void hal_timerInitCore(const unsigned int id);
+
 struct cpu_feature_t {
 	const char *name;
 	s32 eax;
@@ -302,7 +304,7 @@ unsigned int hal_cpuGetCount(void)
 static inline unsigned int _hal_cpuGetID(void)
 {
 	if (hal_isLapicPresent() == 1) {
-		return (*(volatile u32 *)(hal_config.localApicAddr + LAPIC_ID_REG)) >> 24;
+		return _hal_lapicRead(LAPIC_ID_REG) >> 24;
 	}
 	else {
 		return 0;
@@ -326,26 +328,22 @@ unsigned int hal_cpuGetID(void)
 /* Sends IPI to everyone but self */
 void cpu_broadcastIPI(unsigned int intr)
 {
-	volatile u32 *p;
 	if (hal_isLapicPresent() == 1) {
-		p = hal_config.localApicAddr + LAPIC_ICR_REG_0_31;
-		*p = intr | 0xc4000;
-		while (*p & (1 << 12)) {
+		_hal_lapicWrite(LAPIC_ICR_REG_0_31, intr | 0xc4000);
+		while ((_hal_lapicRead(LAPIC_ICR_REG_0_31) & (1 << 12)) != 0) {
 		}
 	}
 }
 
 
 void hal_cpuSendIPI(unsigned int cpu, unsigned int intrAndFlags)
 {
-	volatile u32 *p, *q;
 	if (hal_isLapicPresent() == 1) {
-		p = hal_config.localApicAddr + LAPIC_ICR_REG_0_31;
-		q = hal_config.localApicAddr + LAPIC_ICR_REG_32_63;
 		/* Set destination */
-		*q = (cpu & 0xff) << 24;
-		*p = intrAndFlags & 0xcdfff;
-		while (*p & (1 << 12)) {
+		/* TODO: Disable interrupts while we're writing */
+		_hal_lapicWrite(LAPIC_ICR_REG_32_63, (cpu & 0xff) << 24);
+		_hal_lapicWrite(LAPIC_ICR_REG_0_31, intrAndFlags & 0xcdfff);
+		while ((_hal_lapicRead(LAPIC_ICR_REG_0_31) & (1 << 12)) != 0) {
 		}
 	}
 }
@@ -377,13 +375,11 @@ static void _cpu_gdtInsert(unsigned int idx, u32 base, u32 limit, u32 type)
 
 void *_cpu_initCore(void)
 {
-	volatile u32 *p;
 	const unsigned int id = hal_cpuGetID();
 	hal_cpuAtomAdd(&cpu.readyCount, 1);
 
 	if (hal_isLapicPresent() == 1) {
-		p = hal_config.localApicAddr + LAPIC_SPUR_IRQ_REG;
-		*p = (*p | 0x11ffu);
+		_hal_lapicWrite(LAPIC_SPUR_IRQ_REG, _hal_lapicRead(LAPIC_SPUR_IRQ_REG) | 0x11ffu);
 	}
 
 	hal_memset(&cpu.tss[id], 0, sizeof(tss_t));
@@ -420,6 +416,7 @@ void *_cpu_initCore(void)
 	/* clang-format on */
 
 	hal_tlbInitCore(id);
+	hal_timerInitCore(id);
 
 	return (void *)cpu.tss[id].esp0;
 }
@@ -433,6 +430,7 @@ static void _hal_cpuInitCores(void)
 
 	/* Initialize BSP */
 	cpu.readyCount = 0;
+	_hal_timerInit(SYSTICK_INTERVAL);
 	_cpu_initCore();
 
 	*(u32 *)(syspage->hs.stack + VADDR_KERNEL - 4) = 0;

diff --git a/hal/ia32/hal.c b/hal/ia32/hal.c
@@ -76,7 +76,6 @@ void _hal_init(void)
 	_hal_interruptsInit();
 
 	_hal_cpuInit();
-	_hal_timerInit(SYSTICK_INTERVAL);
 	_hal_pciInit();
 
 	hal_common.started = 0;

diff --git a/hal/ia32/init.h b/hal/ia32/init.h
@@ -186,6 +186,18 @@ static inline int hal_isLapicPresent(void)
 }
 
 
+static inline void _hal_lapicWrite(u32 reg, u32 value)
+{
+	*(volatile u32 *)(hal_config.localApicAddr + reg) = value;
+}
+
+
+static inline u32 _hal_lapicRead(u32 reg)
+{
+	return *(volatile u32 *)(hal_config.localApicAddr + reg);
+}
+
+
 void _hal_configInit(syspage_t *s);
 
 

diff --git a/hal/ia32/interrupts.c b/hal/ia32/interrupts.c
@@ -163,14 +163,13 @@ static inline void _hal_ioapicRoundRobin(unsigned int n)
 
 static inline void _hal_interrupts_8259EOI(unsigned int n)
 {
-	volatile u32 *p = hal_config.localApicAddr + LAPIC_EOI_REG;
 	if ((hal_isLapicPresent() != 0) && (n == TLB_IRQ)) {
-		*p = 0;
+		_hal_lapicWrite(LAPIC_EOI_REG, LAPIC_EOI);
 		return;
 	}
 	/* Check for rare case, when we use 8259 PIC with multiple cores and APIC */
 	if (hal_cpuGetID() != 0) {
-		*p = 0;
+		_hal_lapicWrite(LAPIC_EOI_REG, LAPIC_EOI);
 		return;
 	}
 	if (n < 8) {
@@ -185,9 +184,8 @@ static inline void _hal_interrupts_8259EOI(unsigned int n)
 
 static inline void _hal_interruptsApicEOI(unsigned int n)
 {
-	volatile u32 *p = hal_config.localApicAddr + LAPIC_EOI_REG;
 	_hal_ioapicRoundRobin(n);
-	*p = 0;
+	_hal_lapicWrite(LAPIC_EOI_REG, LAPIC_EOI);
 }