add gr712rc target

refactor gaisler cpu support to be more generic

JIRA: RTOS-616

devices/uart-grlib/uart.c

@@ -243,7 +243,9 @@ static int uart_done(unsigned int minor)
 	*(uart->base + uart_scaler) = 0;
 	hal_cpuDataStoreBarrier();
 
+#ifdef __CPU_GR716
 	_gr716_cguClkDisable(cgu_primary, cgudev_apbuart0 + minor);
+#endif
 
 	hal_interruptsSet(uart->irq, NULL, NULL);
 
@@ -290,16 +292,18 @@ static int uart_init(unsigned int minor)
 
 	uart_done(minor);
 
+#ifdef __CPU_GR716
 	_gr716_cguClkEnable(cgu_primary, cgudev_apbuart0 + minor);
+#endif
 
 	cfg.opt = 0x1;
 	cfg.pullup = 0;
 	cfg.pulldn = 0;
 	cfg.pin = info[minor].txPin;
-	_gr716_iomuxCfg(&cfg);
+	gaisler_iomuxCfg(&cfg);
 
 	cfg.pin = info[minor].rxPin;
-	_gr716_iomuxCfg(&cfg);
+	gaisler_iomuxCfg(&cfg);
 
 	lib_cbufInit(&uart->cbuffRx, uart->dataRx, BUFFER_SIZE);
 

hal/sparcv8leon3/Makefile

@@ -6,8 +6,6 @@
 # %LICENSE%
 #
 
-include hal/sparcv8leon3/$(TARGET_SUBFAMILY)/Makefile
+include hal/sparcv8leon3/gaisler/Makefile
 
-CFLAGS += -Ihal/sparcv8leon3/$(TARGET_SUBFAMILY)
-
-OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/, cpu.o string.o interrupts.o exceptions.o _init.o _interrupts.o _traps.o)
+OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/, string.o interrupts.o exceptions.o _interrupts.o _traps.o)

hal/sparcv8leon3/_interrupts.S

@@ -99,7 +99,11 @@ wovfl_done:
 	mov %l3, %o0
 
 	/* Disable traps, we can't let a trap use the free stack space */
+#ifndef __CPU_GR712RC
 	pwr 0, %psr
+#else
+	wr %l0, %psr
+#endif
 	nop
 	nop
 	nop
@@ -163,11 +167,33 @@ cwp_done:
 	save
 
 wufl_done:
+
+#ifdef LEON3_TN_0018_FIX
+1:
+	/* Wait for ICache flush to complete */
+	lda [%g0] ASI_CCTRL, %l3
+	srl %l3, 15, %l4   /* ICache flush pending bit */
+	andcc %l4, 1, %g0
+	bne 1b
+	andn %l3, 0x3, %l4 /* ICache state */
+#endif
+
 	/* restore %psr */
 	wr %l0, %psr
 	nop
 	nop
 	nop
+
+#ifdef LEON3_TN_0018_FIX
+.align 0x20                  /* Align sta for performance */
+	sta %l4, [%g0] ASI_CCTRL /* Disable ICache */
+	nop                      /* Delay */
+	or %l1, %l1, %l1         /* Delay + catch rf parity error on l1 */
+	or %l2, %l2, %l2         /* Delay + catch rf parity error on l2 */
+	sta %l3, [%g0] ASI_CCTRL /* Re-enable ICache after rett */
+	nop                      /* Delay ensures insn after gets cached */
+#endif
+
 	jmp %l1
 	rett %l2
 

hal/sparcv8leon3/_traps.S

@@ -156,6 +156,8 @@ _start:
 .section ".text"
 .align 4
 
+/* Underflow/overflow traps never return directly to 'jmpl' instruction - no TN-0018 fix needed */
+
 /* Window underflow handler
 * on entry:
 * %psr in %l0, PC in %l1, nPC in %l2
@@ -236,6 +238,7 @@ _traps_setPil:
 	nop
 	nop
 	nop
+	/* TN-0018 fix done after 'ta' instruction */
 	jmp %l2
 	rett %l2 + 4
 .size _traps_setPil, . - _traps_setPil
@@ -307,7 +310,8 @@ _exceptions_dispatch:
 	nop
 
 	/* trap type */
-	and %g1, TBR_TT_MSK, %o0
+	set TBR_TT_MSK, %g2
+	and %g1, %g2, %o0
 	srl %o0, TBR_TT_SHIFT, %o0
 
 	/* void exceptions_dispatch(unsigned int n, exc_context_t *ctx) */

hal/sparcv8leon3/cpu.h

@@ -41,13 +41,6 @@
 #include <peripherals.h>
 
 
-static inline void hal_cpuHalt(void)
-{
-	/* must be performed in supervisor mode with int enabled */
-	__asm__ volatile("wr %g0, %asr19");
-}
-
-
 static inline void hal_cpuDataStoreBarrier(void)
 {
 	__asm__ volatile("stbar");

hal/sparcv8leon3/gaisler/Makefile

@@ -0,0 +1,19 @@
+#
+# Makefile for Phoenix-RTOS loader (SPARCV8 LEON3 HAL)
+#
+# Copyright 2023 Phoenix Systems
+#
+# %LICENSE%
+#
+
+CFLAGS += -Ihal/sparcv8leon3/gaisler/ -Ihal/sparcv8leon3/gaisler/$(TARGET_SUBFAMILY)
+
+include hal/sparcv8leon3/gaisler/$(TARGET_SUBFAMILY)/Makefile
+
+OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/gaisler/, console.o timer.o)
+
+ifeq ($(TARGET_SUBFAMILY), gr712rc)
+  OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/gaisler/, irqmp.o)
+else ifeq ($(TARGET_SUBFAMILY), gr716)
+  OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/gaisler/, irqamp.o)
+endif

hal/sparcv8leon3/gr716/console.c → hal/sparcv8leon3/gaisler/console.c

@@ -14,18 +14,19 @@
  */
 
 #include <hal/hal.h>
-#include <devices/gpio-gr716/gpio.h>
-
 
 /* UART control bits */
 #define TX_EN        (1 << 1)
 #define TX_FIFO_FULL (1 << 9)
 
+#define CONCAT_(a, b) a##b
+#define CONCAT(a, b)  CONCAT_(a, b)
+
 /* Console config */
-#define UART_CONSOLE_RX   UART2_RX
-#define UART_CONSOLE_TX   UART2_TX
-#define UART_CONSOLE_BASE UART2_BASE
-#define UART_CONSOLE_CGU  cgudev_apbuart2
+#define UART_CONSOLE_RX   CONCAT(UART, CONCAT(UART_CONSOLE_PLO, _RX))
+#define UART_CONSOLE_TX   CONCAT(UART, CONCAT(UART_CONSOLE_PLO, _TX))
+#define UART_CONSOLE_BASE CONCAT(UART, CONCAT(UART_CONSOLE_PLO, _BASE))
+#define UART_CONSOLE_CGU  CONCAT(cgudev_apbuart, UART_CONSOLE_PLO)
 
 
 enum {
@@ -68,12 +69,15 @@ void console_init(void)
 	cfg.pullup = 0;
 	cfg.pulldn = 0;
 	cfg.pin = UART_CONSOLE_TX;
-	_gr716_iomuxCfg(&cfg);
+	gaisler_iomuxCfg(&cfg);
 
 	cfg.pin = UART_CONSOLE_RX;
-	_gr716_iomuxCfg(&cfg);
+	gaisler_iomuxCfg(&cfg);
 
+#ifdef __CPU_GR716
 	_gr716_cguClkEnable(cgu_primary, UART_CONSOLE_CGU);
+#endif
+
 	halconsole_common.uart = UART_CONSOLE_BASE;
 	*(halconsole_common.uart + uart_ctrl) = TX_EN;
 	*(halconsole_common.uart + uart_scaler) = console_calcScaler(UART_BAUDRATE);

hal/sparcv8leon3/gaisler/gaisler.h

@@ -0,0 +1,34 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system loader
+ *
+ * Gaisler CPU specific functions
+ *
+ * Copyright 2023 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _GAISLER_H_
+#define _GAISLER_H_
+
+
+#include "types.h"
+
+
+typedef struct {
+	u8 pin;
+	u8 opt;
+	u8 pullup;
+	u8 pulldn;
+} iomux_cfg_t;
+
+
+int gaisler_iomuxCfg(iomux_cfg_t *ioCfg);
+
+
+#endif

hal/sparcv8leon3/gaisler/gr712rc/Makefile

@@ -0,0 +1,16 @@
+#
+# Makefile for Phoenix-RTOS loader (SPARCV8 LEON3 GR712RC HAL)
+#
+# Copyright 2023 Phoenix Systems
+#
+# %LICENSE%
+#
+
+CFLAGS += -DVADDR_KERNEL_INIT=$(VADDR_KERNEL_INIT)
+
+PLO_COMMANDS := alias app call console copy dump echo go help kernel map mem phfs reboot script wait
+
+include devices/uart-grlib/Makefile
+include devices/ram-storage/Makefile
+
+OBJS += $(addprefix $(PREFIX_O)hal/$(TARGET_SUFF)/gaisler/$(TARGET_SUBFAMILY)/, _init.o hal.o gr712rc.o)

hal/sparcv8leon3/gaisler/gr712rc/_init.S

@@ -0,0 +1,62 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system loader
+ *
+ * Low level initialization
+ *
+ * Copyright 2022-2023 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+ #define __ASSEMBLY__
+
+#include "config.h"
+#include "../../cpu.h"
+
+
+.section ".init", "ax"
+.align 4
+.global _init
+.type _init, #function
+_init:
+	wr %g0, %wim
+	nop
+	nop
+	nop
+
+	wr %g0, PSR_S, %psr
+
+	/* Set up trap table */
+	sethi %hi(_trap_table), %g1
+	wr %g1, %tbr
+
+	wr %g0, 0x2, %wim
+
+	/* Flush and enable cache - section 4.5.7 GR712RC UM */
+	flush
+	set 0x81000f, %g1
+	sta %g1, [%g0] ASI_CCTRL
+
+	clr %fp
+
+	/* Stack pointer */
+	set _stack, %sp
+	sub %sp, 0x60, %sp
+
+	/* Set PSR to supervisor, enable traps, disable irq */
+	wr %g0, (PSR_ET | PSR_S | PSR_PIL), %psr
+	nop
+	nop
+	nop
+
+	wr %g0, 0x2, %wim
+
+	sethi %hi(_startc), %g1
+	jmpl %g1 + %lo(_startc), %g0
+	clr %g1
+.size _init, . - _init

hal/sparcv8leon3/gaisler/gr712rc/config.h

@@ -0,0 +1,44 @@
+/*
+ * Phoenix-RTOS
+ *
+ * Operating system loader
+ *
+ * Platform configuration
+ *
+ * Copyright 2022-2023 Phoenix Systems
+ * Author: Lukasz Leczkowski
+ *
+ * This file is part of Phoenix-RTOS.
+ *
+ * %LICENSE%
+ */
+
+#ifndef _CONFIG_H_
+#define _CONFIG_H_
+
+
+#ifndef __ASSEMBLY__
+
+#include "gr712rc.h"
+#include "peripherals.h"
+#include "../gaisler.h"
+#include "../types.h"
+#include "../../cpu.h"
+
+#include <phoenix/arch/syspage-sparcv8leon3.h>
+#include <phoenix/syspage.h>
+
+#define PATH_KERNEL "phoenix-sparcv8leon3-gr712rc.elf"
+
+#endif /* __ASSEMBLY__ */
+
+
+#define NWINDOWS 8
+
+#define ASI_CCTRL 0x02
+
+/* Import platform specific definitions */
+#include "ld/sparcv8leon3-gr712rc.ldt"
+
+
+#endif