Merge pull request #198 from riscv/zfinx-soft-float-abi

Add a note to call out that Zfinx always follows the "soft-float" ABI
riscv-non-isa · Jul 28, 2021 · 8f4d51f · 8f4d51f
2 parents adc22e3 + d573fdd
commit 8f4d51f
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/riscv-elf.md b/riscv-elf.md
@@ -322,6 +322,11 @@ operating mode.
 The \*F ABIs require the \*F ISA extension, the \*D ABIs require the \*D ISA
 extension, and the LP64Q ABI requires the Q ISA extension.
 
+> NOTE:
+> This means code targeting the Zfinx extension always uses the ILP32, ILP32E
+> or LP64 integer calling-convention only ABIs as there is no dedicated
+> hardware floating-point register file.
+
 ## <a name=default-abis></a>Default ABIs
 
 While various different ABIs are technically possible, for software