EF_RISCV_RV64ILP32: Support ILP32 ABI on RV64 ISA

riscv-cc.adoc

@@ -449,6 +449,16 @@ The ILP32E calling convention is not compatible with ISAs that have registers
 that require load and store alignments of more than 32 bits. In particular, this
 calling convention must not be used with the D ISA extension.
 
+=== RV64ILP32 Calling Convention (experimental)
+
+IMPORTANT: RV64ILP32 is not a ratified base ISA and so we cannot guarantee the
+stability of RV64ILP32, in contrast with the rest of this document. This documents
+the current implementation in GCC as of the time of writing, but may be subject
+to change.
+
+The RV64ILP32 calling convention is designed to be usable with ILP32 ABI the 
+RV64 ISA. This calling convention is the same as the integer calling convention. 
+
 === Named ABIs
 
 This specification defines the following named ABIs:
@@ -493,10 +503,8 @@ LP64Q:: LP64 with hardware floating-point calling
 convention for ABI_FLEN=128 (i.e. <<ELFCLASS64,ELFCLASS64>> and
 <<EF_RISCV_FLOAT_ABI_QUAD,EF_RISCV_FLOAT_ABI_QUAD>>).
 
-The ILP32* ABIs are only compatible with RV32* ISAs, and the LP64* ABIs are
-only compatible with RV64* ISAs. A future version of this specification may
-define an ILP32 ABI for the RV64 ISA, but currently this is not a supported
-operating mode.
+The LP64* ABIs are only compatible with RV64* ISAs. The ILP32* are compatible 
+with RV32* and RV64* ISAs. Note: RV64* with ILP32 ABI is experimental.
 
 The *F ABIs require the *F ISA extension, the *D ABIs require the *D ISA
 extension, and the LP64Q ABI requires the Q ISA extension.
@@ -535,7 +543,7 @@ There are two conventions for C/{Cpp} type sizes and alignments.
 ILP32, ILP32F, ILP32D, and ILP32E:: Use the following type sizes and
 alignments (based on the ILP32 convention):
 +
-.C/{Cpp} type sizes and alignments for RV32
+.C/{Cpp} type sizes and alignments for ILP32
 [cols="4,>2,>3,4"]
 [width=60%]
 |===
@@ -561,7 +569,7 @@ alignments (based on the ILP32 convention):
 LP64, LP64F, LP64D, and LP64Q:: Use the following type sizes and
 alignments (based on the LP64 convention):
 +
-.C/{Cpp} type sizes and alignments for RV64
+.C/{Cpp} type sizes and alignments for LP64
 [cols="4,>2,>3,4"]
 [width=60%]
 |===

riscv-elf.adoc

@@ -26,6 +26,11 @@ address space or the lower 2 GiB and highest 2 GiB of the RV64 address space
 By using the `lui` and load / store instructions, when referring to an object, or
 `addi`, when calculating an address literal, for example,
 a 32-bit address literal can be produced.
+For the ILP32 ABI on RV64* ISA, the medlow allows the code to address lower 2GiB
+of the RV64 address space (`0x0` ~ `0x000000007FFFFFFF`).
+
+NOTE: Limiting the address space to lower 2GiB does not pose any issues with sign
+extending addresses into the upper 32 bits of a 64-bit register.
 
 The following instructions show how to load a value, store a value, or calculate
 an address in the `medlow` code model.
@@ -277,12 +282,12 @@ below.
 +
 [[e-flags-layout]]
 .Layout of e_flags
-[cols="1,2,1,1,3,5"]
+[cols="1,2,1,1,1,3,5"]
 [width=80%]
 |===
-| Bit 0 | Bits 1 - 2 | Bit 3 | Bit 4 | Bits 5 - 23 | Bits 24 - 31
+| Bit 0 | Bits 1 - 2 | Bit 3 | Bit 4 | Bit 5 | Bits 6 - 23 | Bits 24 - 31
 
-| RVC   | Float ABI  | RVE   | TSO   | *Reserved*  | *Non-standard extensions*
+| RVC   | Float ABI  | RVE   | TSO   | RV64ILP32    | *Reserved*  | *Non-standard extensions*
 |===
 
 +
@@ -320,6 +325,9 @@ below.
   EF_RISCV_TSO (0x0010)::: This bit is set when the binary requires the RVTSO
   memory consistency model.
 
+  EF_RISCV_RV64ILP32 (0x0020)::: This bit is set when the binary requires the ILP32*
+  ABI on RV64* ISAs. Note: RV64* ISAs with ILP32 ABI are experimental.
+
 Until such a time that the *Reserved* bits (0x00ffffe0) are allocated by future
 versions of this specification, they shall not be set by standard software.
 Non-standard extensions are free to use bits 24-31 for any purpose. This may
@@ -355,6 +363,9 @@ raise an error.
   TSO::: Input files can have different values for the TSO field; the linker
   should set this field if any of the input objects have the TSO field set.
 
+  RV64ILP32::: Linker should report errors if object files of different value
+  for RV64ILP32  field.
+
 NOTE: The static linker may ignore the compatibility checks if all fields in the
 `e_flags` are zero and all sections in the input file are non-executable
 sections.