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Switch all wavedrom diagrams to output svg images. #110

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Jun 1, 2023
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Switch all wavedrom diagrams to output svg images. #110

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12 changes: 6 additions & 6 deletions cfi_backward.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -133,7 +133,7 @@ A shadow stack pop operation is defined as a `XLEN` wide read from the
current top of the shadow stack followed by an increment of the `ssp` by
`XLEN`.

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand All @@ -144,7 +144,7 @@ current top of the shadow stack followed by an increment of the `ssp` by
], config:{lanes: 1, hspace:1024}}
....

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand All @@ -155,7 +155,7 @@ current top of the shadow stack followed by an increment of the `ssp` by
], config:{lanes: 1, hspace:1024}}
....

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand All @@ -167,7 +167,7 @@ current top of the shadow stack followed by an increment of the `ssp` by
], config:{lanes: 1, hspace:1024}}
....

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 2, name: 'op', attr:'C1'},
Expand Down Expand Up @@ -561,7 +561,7 @@ back_cfi_not_enabled:
The `ssprr` instruction is provided to move the contents of `ssp` to the destination
register.

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand Down Expand Up @@ -613,7 +613,7 @@ bits of the `src` register and the `XLEN` bits located on the shadow stack at th
address specified in the `addr` register. The resulting value from the swap
operation is then stored into the register specified in the `dst` operand.

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand Down
14 changes: 7 additions & 7 deletions cfi_csrs.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ This chapter specifies the CSR state of the Zicfisslp extension.
=== Machine environment configuration registers (`menvcfg and menvcfgh`)

.Machine environment configuration register (`menvcfg`) for MXLEN=64
[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'FIOM'},
Expand Down Expand Up @@ -57,7 +57,7 @@ backward-edge and forward-edge CFI at S-mode and at U-mode for each application.
=== Hypervisor environment configuration registers (`henvcfg and henvcfgh`)

.Hypervisor environment configuration register (`henvcfg`) for MXLEN=64
[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'FIOM'},
Expand Down Expand Up @@ -92,7 +92,7 @@ forward-edge CFI at VS-mode.
=== Machine status registers (`mstatus`)

.Machine-mode status register (`mstatus`) for RV64
[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
Expand Down Expand Up @@ -141,7 +141,7 @@ encoded as follows:
=== Supervisor status registers (`sstatus`)

.Supervisor-mode status register (`sstatus`) when `SXLEN=64`
[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
Expand Down Expand Up @@ -180,7 +180,7 @@ read-only zero.
=== Virtual supervisor status registers (`vsstatus`)

.Virtual supervisor status register (`vsstatus`) when `VSXLEN=64`
[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
Expand Down Expand Up @@ -229,7 +229,7 @@ in `vsstatus` when the CSR is accessed in HS-mode.
=== Machine Security Configuration (`mseccfg`)

.Machine security configuration register (`mseccfg`) when `MXLEN=64`
[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'MML'},
Expand Down Expand Up @@ -259,7 +259,7 @@ is split into an 8-bit upper label (`UL`), an 8-bit middle label (`ML`), and a
9-bit lower label (`LL`).

.`lpl` for RV32 and RV64
[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 9, name: 'LL'},
Expand Down
8 changes: 4 additions & 4 deletions cfi_forward.adoc
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Expand Up @@ -182,7 +182,7 @@ The `lpcll` has the lower landing pad label embedded in the `LLPL` field.
`lpcll` causes an illegal-instruction exception if the `LLPL` field in the
instruction does not match the `lpl.LL` field.

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand Down Expand Up @@ -246,7 +246,7 @@ The `lpcul` instruction matches the 8-bit wide upper label in its `ULPL` field w
the `lpl.UL` field and causes an illegal-instruction exception on a mismatch. The
`lpcul` is not a valid target for an indirect call or jump.

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand Down Expand Up @@ -291,7 +291,7 @@ Before performing an indirect call or indirect jump to a labeled landing pad,
the `lpl` is loaded with the expected landing pad label. The label is a constant
encoded into the instructions used to setup the `lpl`.

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand All @@ -303,7 +303,7 @@ encoded into the instructions used to setup the `lpl`.
], config:{lanes: 1, hspace:1024}}
....

[wavedrom, , ]
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr:'SYSTEM'},
Expand Down
Binary file modified riscv-cfi.pdf
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