release the constraint to enable e8mf8 in EEW=32

e8mf8 type is allowed when VLEN>=64 and EEW=32, the common case of VLEN is VLEN>EEW, e.g. VLEN=64/128/256, and EEW=32.

Signed-off-by: Jiuyang Liu <liu@jiuyang.me>

src/v-st-ext.adoc

@@ -274,19 +274,18 @@ register-resident vectors.
 Implementations must provide fractional LMUL settings that allow the
 narrowest supported type to occupy a fraction of a vector register
 corresponding to the ratio of the narrowest supported type's width to
-that of the largest supported type's width.  In general, the
-requirement is to support LMUL {ge} SEW~MIN~/ELEN, where SEW~MIN~ is
-the narrowest supported SEW value and ELEN is the widest supported SEW
-value.  In the standard extensions, SEW~MIN~=8.  For
-standard vector extensions with ELEN=32, fractional LMULs of 1/2 and
-1/4 must be supported.  For standard vector extensions with ELEN=64,
-fractional LMULs of 1/2, 1/4, and 1/8 must be supported.
-
-NOTE: When LMUL < SEW~MIN~/ELEN, there is no guarantee
+that of the vector register width.  In general, the requirement is to 
+support LMUL {ge} SEW~MIN~/VLEN, where SEW~MIN~ is the narrowest supported
+SEW value and VLEN is the length of vector register.  In the standard
+extensions, SEW~MIN~=8.  For standard vector extensions with VLEN=32,
+fractional LMULs of 1/2 and 1/4 must be supported.  For standard vector 
+extensions with VLEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be
+supported.
+
+NOTE: When LMUL < SEW~MIN~/VLEN, there is no guarantee
 an implementation would have enough bits in the fractional vector
-register to store at least one element, as VLEN=ELEN is a
-valid implementation choice. For example, with VLEN=ELEN=32,
-and SEW~MIN~=8, an LMUL of 1/8 would only provide four bits of
+register to store at least one element, as VLEN=ELEN=32, SEW~MIN~=8 is a 
+valid implementation choice, an LMUL of 1/8 would only provide four bits of
 storage in a vector register.
 
 For a given supported fractional LMUL setting, implementations must support