Add additional ELF flags.

librz/bin/format/elf/glibc_elf.h

@@ -4080,6 +4080,9 @@ enum {
 #define ET_HEXAGON_IR 0xff00
 
 /* Values for Elf32_Ehdr.e_flags.  */
+/* Object processor version flags, bits[11:0] */
+#define EF_HEXAGON_MACH_V2   0x1
+#define EF_HEXAGON_MACH_V3   0x2
 #define EF_HEXAGON_MACH_V4   0x3
 #define EF_HEXAGON_MACH_V5   0x4
 #define EF_HEXAGON_MACH_V55  0x5
@@ -4090,6 +4093,21 @@ enum {
 #define EF_HEXAGON_MACH_V66  0x66
 #define EF_HEXAGON_MACH_V67  0x67
 #define EF_HEXAGON_MACH_V67T 0x8067 /* Hexagon V67 Small Core (V67t) */
+#define EF_HEXAGON_MACH_V68  = 0x68
+
+/* Highest ISA version flags */
+#define EF_HEXAGON_ISA_MACH 0x0 /* Same as specified in bits[11:0] of e_flags */
+#define EF_HEXAGON_ISA_V2   0x10
+#define EF_HEXAGON_ISA_V3   0x20
+#define EF_HEXAGON_ISA_V4   0x30
+#define EF_HEXAGON_ISA_V5   0x40
+#define EF_HEXAGON_ISA_V55  0x50
+#define EF_HEXAGON_ISA_V60  0x60
+#define EF_HEXAGON_ISA_V62  0x62
+#define EF_HEXAGON_ISA_V65  0x65
+#define EF_HEXAGON_ISA_V66  0x66
+#define EF_HEXAGON_ISA_V67  0x67
+#define EF_HEXAGON_ISA_V68  0x68
 
 /* Special section indices.  */
 #define SHN_HEXAGON_SCOMMON   0xff00 /* Other access sizes */
@@ -4101,6 +4119,9 @@ enum {
 /* Legal values for sh_flags (section flags).  */
 #define SHF_HEXAGON_GPREL 0x10000000 /* Section resides in the small data area */
 
+/* Legal values for sh_type (section type).  */
+#define SHT_HEX_ORDERED 0x70000000 /* Link editor is to sort the entries in this section based on their sizes. */
+
 /* Qualcomm QDSP6 relocations */
 /*          Name             Value      Field       Relocation            Result   Action */
 #define R_HEX_NONE               0 /*  None        None                  None     None */