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Handle more 64bit shifts in Translator #1825

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22 changes: 21 additions & 1 deletion src/shader_recompiler/frontend/translate/scalar_alu.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -72,10 +72,14 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
return S_OR_B64(NegateMode::Result, true, inst);
case Opcode::S_LSHL_B32:
return S_LSHL_B32(inst);
case Opcode::S_LSHL_B64:
return S_LSHL_B64(inst);
case Opcode::S_LSHR_B32:
return S_LSHR_B32(inst);
case Opcode::S_ASHR_I32:
return S_ASHR_I32(inst);
case Opcode::S_ASHR_I64:
return S_ASHR_I64(inst);
case Opcode::S_BFM_B32:
return S_BFM_B32(inst);
case Opcode::S_MUL_I32:
Expand Down Expand Up @@ -412,6 +416,14 @@ void Translator::S_LSHL_B32(const GcnInst& inst) {
ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
}

void Translator::S_LSHL_B64(const GcnInst& inst) {
const IR::U64 src0{GetSrc64(inst.src[0])};
const IR::U64 src1{GetSrc64(inst.src[1])};
const IR::U64 result = ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F))));
SetDst64(inst.dst[0], result);
ir.SetScc(ir.INotEqual(result, ir.Imm64(u64(0))));
}

void Translator::S_LSHR_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
Expand All @@ -423,11 +435,19 @@ void Translator::S_LSHR_B32(const GcnInst& inst) {
void Translator::S_ASHR_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
const IR::U32 result{ir.ShiftRightArithmetic(src0, src1)};
const IR::U32 result{ir.ShiftRightArithmetic(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F)))};
SetDst(inst.dst[0], result);
ir.SetScc(ir.INotEqual(result, ir.Imm32(0)));
}

void Translator::S_ASHR_I64(const GcnInst& inst) {
const IR::U64 src0{GetSrc64(inst.src[0])};
const IR::U64 src1{GetSrc64(inst.src[1])};
const IR::U64 result{ir.ShiftRightArithmetic(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F))))};
SetDst64(inst.dst[0], result);
ir.SetScc(ir.INotEqual(result, ir.Imm64(u64(0))));
}

void Translator::S_BFM_B32(const GcnInst& inst) {
const IR::U32 src0{ir.BitwiseAnd(GetSrc(inst.src[0]), ir.Imm32(0x1F))};
const IR::U32 src1{ir.BitwiseAnd(GetSrc(inst.src[1]), ir.Imm32(0x1F))};
Expand Down
2 changes: 2 additions & 0 deletions src/shader_recompiler/frontend/translate/translate.h
Original file line number Diff line number Diff line change
Expand Up @@ -90,8 +90,10 @@ class Translator {
void S_OR_B64(NegateMode negate, bool is_xor, const GcnInst& inst);
void S_XOR_B32(const GcnInst& inst);
void S_LSHL_B32(const GcnInst& inst);
void S_LSHL_B64(const GcnInst& inst);
void S_LSHR_B32(const GcnInst& inst);
void S_ASHR_I32(const GcnInst& inst);
void S_ASHR_I64(const GcnInst& inst);
void S_BFM_B32(const GcnInst& inst);
void S_MUL_I32(const GcnInst& inst);
void S_BFE(const GcnInst& inst, bool is_signed);
Expand Down
4 changes: 4 additions & 0 deletions src/shader_recompiler/frontend/translate/vector_alu.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1211,6 +1211,10 @@ void Translator::V_LSHL_B64(const GcnInst& inst) {
ir.SetVectorReg(dst_reg + 1, ir.Imm32(static_cast<u32>(result >> 32)));
return;
}

const IR::U64 result = ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F))));
SetDst64(inst.dst[0], result);
return;
}
UNREACHABLE_MSG("Unimplemented V_LSHL_B64 arguments");
}
Expand Down
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