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Implement flags for RDNA instructions #728

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Implement flags for RDNA instructions #728

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8eb6b57
Implement overflow flag for S_ADD_I32
OFFTKP Sep 2, 2024
b331f24
Implement S_SUB_I32 and flags for S_SUB_U32
OFFTKP Sep 2, 2024
0491ceb
Set unsigned overflow flag for S_ADD_U32
OFFTKP Sep 2, 2024
aee5307
Match the coding style a bit more
OFFTKP Sep 2, 2024
5f6a9d0
Set carry for S_ADDC_U32
OFFTKP Sep 2, 2024
0d81774
Set overflow flag for V_ADD_I32
OFFTKP Sep 2, 2024
616910f
Set overflow flag for V_SUBREV_I32
OFFTKP Sep 2, 2024
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39 changes: 30 additions & 9 deletions src/shader_recompiler/frontend/translate/scalar_alu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -70,8 +70,9 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
case Opcode::S_ADDC_U32:
return S_ADDC_U32(inst);
case Opcode::S_SUB_U32:
case Opcode::S_SUB_I32:
return S_SUB_U32(inst);
case Opcode::S_SUB_I32:
return S_SUB_I32(inst);
case Opcode::S_MIN_U32:
return S_MIN_U32(inst);
case Opcode::S_MAX_U32:
Expand Down Expand Up @@ -373,8 +374,13 @@ void Translator::S_AND_B64(NegateMode negate, const GcnInst& inst) {
void Translator::S_ADD_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst(inst.dst[0], ir.IAdd(src0, src1));
// TODO: Overflow flag
const IR::U32 result{ir.IAdd(src0, src1)};
SetDst(inst.dst[0], result);
const IR::U32 sign_mask{ir.Imm32(1 << 31)};
const IR::U32 sign0{ir.BitwiseAnd(src0, sign_mask)};
const IR::U32 sign1{ir.BitwiseAnd(src1, sign_mask)};
const IR::U32 signr{ir.BitwiseAnd(result, sign_mask)};
ir.SetScc(ir.LogicalAnd(ir.IEqual(sign0, sign1), ir.INotEqual(sign0, signr)));
}

void Translator::S_AND_B32(const GcnInst& inst) {
Expand Down Expand Up @@ -505,17 +511,28 @@ void Translator::S_BREV_B32(const GcnInst& inst) {
void Translator::S_ADD_U32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst(inst.dst[0], ir.IAdd(src0, src1));
// TODO: Carry out
ir.SetScc(ir.Imm1(false));
const IR::U32 result{ir.IAdd(src0, src1)};
SetDst(inst.dst[0], result);
ir.SetScc(ir.ILessThan(result, src0, false));
}

void Translator::S_SUB_U32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst(inst.dst[0], ir.ISub(src0, src1));
// TODO: Carry out
ir.SetScc(ir.Imm1(false));
ir.SetScc(ir.IGreaterThan(src1, src0, false));
}

void Translator::S_SUB_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
const IR::U32 result{ir.ISub(src0, src1)};
SetDst(inst.dst[0], result);
const IR::U32 sign_mask{ir.Imm32(1 << 31)};
const IR::U32 sign0{ir.BitwiseAnd(src0, sign_mask)};
const IR::U32 sign1{ir.BitwiseAnd(src1, sign_mask)};
const IR::U32 signr{ir.BitwiseAnd(result, sign_mask)};
ir.SetScc(ir.LogicalAnd(ir.INotEqual(sign0, sign1), ir.INotEqual(sign0, signr)));
}

void Translator::S_GETPC_B64(u32 pc, const GcnInst& inst) {
Expand All @@ -530,7 +547,11 @@ void Translator::S_ADDC_U32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
const IR::U32 carry{ir.Select(ir.GetScc(), ir.Imm32(1U), ir.Imm32(0U))};
SetDst(inst.dst[0], ir.IAdd(ir.IAdd(src0, src1), carry));
const IR::U32 result{ir.IAdd(ir.IAdd(src0, src1), carry)};
SetDst(inst.dst[0], result);
const IR::U1 less_src0 = ir.ILessThan(result, src0, false);
const IR::U1 less_src1 = ir.ILessThan(result, src1, false);
ir.SetScc(ir.LogicalOr(less_src0, less_src1));
}

void Translator::S_MAX_U32(const GcnInst& inst) {
Expand Down
1 change: 1 addition & 0 deletions src/shader_recompiler/frontend/translate/translate.h
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Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,7 @@ class Translator {
void S_NOT_B64(const GcnInst& inst);
void S_BREV_B32(const GcnInst& inst);
void S_ADD_U32(const GcnInst& inst);
void S_SUB_I32(const GcnInst& inst);
void S_SUB_U32(const GcnInst& inst);
void S_GETPC_B64(u32 pc, const GcnInst& inst);
void S_ADDC_U32(const GcnInst& inst);
Expand Down
18 changes: 14 additions & 4 deletions src/shader_recompiler/frontend/translate/vector_alu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -411,8 +411,13 @@ void Translator::V_ADD_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
const IR::VectorReg dst_reg{inst.dst[0].code};
ir.SetVectorReg(dst_reg, ir.IAdd(src0, src1));
// TODO: Carry
const IR::U32 result{ir.IAdd(src0, src1)};
ir.SetVectorReg(dst_reg, result);
const IR::U32 sign_mask{ir.Imm32(1 << 31)};
const IR::U32 sign0{ir.BitwiseAnd(src0, sign_mask)};
const IR::U32 sign1{ir.BitwiseAnd(src1, sign_mask)};
const IR::U32 signr{ir.BitwiseAnd(result, sign_mask)};
ir.SetVcc(ir.LogicalAnd(ir.IEqual(sign0, sign1), ir.INotEqual(sign0, signr)));
}

void Translator::V_ADDC_U32(const GcnInst& inst) {
Expand Down Expand Up @@ -660,8 +665,13 @@ void Translator::V_SUBREV_F32(const GcnInst& inst) {
void Translator::V_SUBREV_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst(inst.dst[0], ir.ISub(src1, src0));
// TODO: Carry-out
const IR::U32 result{ir.ISub(src1, src0)};
SetDst(inst.dst[0], result);
const IR::U32 sign_mask{ir.Imm32(1 << 31)};
const IR::U32 sign0{ir.BitwiseAnd(src0, sign_mask)};
const IR::U32 sign1{ir.BitwiseAnd(src1, sign_mask)};
const IR::U32 signr{ir.BitwiseAnd(result, sign_mask)};
ir.SetVcc(ir.LogicalAnd(ir.INotEqual(sign0, sign1), ir.INotEqual(sign0, signr)));
}

void Translator::V_MAD_U64_U32(const GcnInst& inst) {
Expand Down
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