RISC-Vlim is a framework for Logic-in-Memory Architectures based on RI5CY from PULP-Platform
-
Updated
May 22, 2023 - Verilog
RISC-Vlim is a framework for Logic-in-Memory Architectures based on RI5CY from PULP-Platform
This project will be the beginning of my research life!
Add a description, image, and links to the logic-in-memory topic page so that developers can more easily learn about it.
To associate your repository with the logic-in-memory topic, visit your repo's landing page and select "manage topics."