In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

MIPS Multicycle CPU design in Verilog

Microprocessor without Interlocked Pipeline Stages with the extra JR, DIV and MFLO instructions implemented.

Processor supporting ARM architecture made in VHDL as a part of COL216 - Computer Architecture

Implemented additional operations for a Multicycle ARM Processor, as presented in Digital Design and Computer Architecture by Harris & Harris

🎓💻University of Tehran Computer Architecture Course Projects - Spring 2021

Minimalist 8 bit multicycle RISC CPU

ARM Multicycle Processor - 32 bit Assembly instructions - VHDL - Arithmetic and Logical operations, Memory read and write - Vivado

Multicycle and pipeline implementations for a RISC architecture in VHDL - EE309 Autumn 2017, IIT Bombay

MultiCycle and Pipelined Processor designed for the course Computer Organisation of TUC

Computer Architecture Lab projects with various fundamental concepts, including multi-cycle MIPS processors and PIC32 microcontroller programming.

多周期CPU(MIPS指令集), 支持其中54条指令. (From 同济大学计算机组成原理课程设计)

Simple Multicycle Processor Similar to MIPS in Verilog

in this project we have implemented MIPS multicycle projects using Vivado

VHDL implementation of multicycle and pipelined RISC architecture - EE309 Autumn 2018, IIT Bombay

Project of a Verilog implementation of a multicycle processor for the discipline of Computer Architeture and Design II

A project to design and simulate a 16-bit RISC Multicycle Processor

multi-cycle-processor based on Micro-Program with systemverilog

A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.

This project implements a 32-bit multicycle MIPS processor in Verilog. The design is based on a multicycle architecture that executes instructions in multiple stages, reducing the complexity of the control logic compared to a single-cycle processor.