⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
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Dec 23, 2024
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synchronous-counter
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basic implementation of logic structures using verilog (revising github)
registers pipo d-flipflop full-adder sipo sequence-detector siso piso verilog-testbenches synchronous-counter priority-encoder jk-flipflop t-flipflop sr-flip-flop full-subtractor half-subtractor
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Feb 29, 2024 - Verilog
Assignment 6, Digital Logic Design Lab, Spring 2021, IIT Bombay
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Mar 21, 2021 - VHDL
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