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This repo includes the SystemVerilog source code of an accelerator for 3rd Gen FHE, and necessary software interfaces.

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zhehongw/3rd_Gen_FHE_ACC

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3rd_Gen_FHE_ACC

This repo includes the SystemVerilog source code of an accelerator for 3rd Gen FHE and a PSI protocol based on it, and necessary software interfaces. This repo is only intended for usage with AWS F1 instance, please make sure you have the correct environment setup. It is currently under close maintenance and will get more in good shape in the future. Please contact Admin in case of licence issues.

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This repo includes the SystemVerilog source code of an accelerator for 3rd Gen FHE, and necessary software interfaces.

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