Development of a Risc-V Microprocessor with a 5-stage pipeline

The repository consists of four works from the discipline "Computer Architecture" at UFRJ, based on the book Computer Organization and Design [1].

Three of these works are related to the main project of the discipline, which is to develop a RISC-V microprocessor with a 5-stage pipeline, using the VHDL language. The goal is to make this microprocessor capable of processing basic assembly instructions, as well as implementing some AVX instructions and enabling the processor to execute them.

References

[1] Patterson, D. A., & Hennessy, J. L. Computer Organization and Design: The Hardware/Software Interface (RISC-V Edition). Morgan Kaufmann Publishers, 2018.