JITx-Inc · plasmajitx · Oct 4, 2024 · Oct 4, 2024
diff --git a/src/bundles/comms.stanza b/src/bundles/comms.stanza
@@ -24,6 +24,8 @@ doc: \<DOC>
 SMBus Bundle
 System Management Bus (SMBus) is a two wire serial communication protocol
 @see http://smbus.org/specs/
+@member SMBALERT#
+@member SMBSUS#
 <DOC>
 public pcb-enum jsl/bundles/comms/SMBUSPins :
   SMBALERT#
@@ -113,6 +115,9 @@ SPI Bundle Pin Names
 A list of possible names for the SPI interface. Note that in order to connect
 SPI interfaces automatically, the constituent pins need to be present on all
 objects to be connected.
+@member SPI-CS
+@member SPI-COPI
+@member SPI-CIPO
 <DOC>
 
 public pcb-enum jsl/bundles/comms/SPIPins :
@@ -250,6 +255,18 @@ public pcb-bundle octal-spi-with-cs-dqs :
 ; UART - Univeral Asynchronous Receiver/Transmitter
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+doc: \<DOC>
+@member UART-DTR
+@member UART-CTS
+@member UART-DCD
+@member UART-RI
+@member UART-DSR
+@member UART-RTS
+@member UART-CK
+@member UART-DE
+@member UART-RX
+@member UART-TX
+<DOC>
 public pcb-enum jsl/bundles/comms/UARTPins :
   UART-DTR
   UART-CTS

diff --git a/src/bundles/debug.stanza b/src/bundles/debug.stanza
@@ -24,6 +24,9 @@ public pcb-bundle jtag :
   port tdo
   port tms
 
+doc: \<DOC>
+@member SWD-SWO
+<DOC>
 public pcb-enum jsl/bundles/debug/SWDPins :
   SWD-SWO ; Trace Output for Serial Wire Debug
 

diff --git a/src/design/settings.stanza b/src/design/settings.stanza
@@ -4,6 +4,11 @@ defpackage jsl/design/settings:
   import jitx
   import jitx/commands
 
+doc: \<DOC>
+@member DensityLevelA
+@member DensityLevelB
+@member DensityLevelC
+<DOC>
 public pcb-enum jsl/design/settings/DensityLevel:
   DensityLevelA
   DensityLevelB

diff --git a/src/landpatterns/BGA/pads.stanza b/src/landpatterns/BGA/pads.stanza
@@ -25,6 +25,8 @@ to distinguish between the typical pad types used in BGA.
 These are sometimes referred to as `Non-Collapsible` and `Collapsible`,
 respectively.
 
+@member SolderMaskDefined
+@member NonSolderMaskDefined
 <DOC>
 public defenum BGAPadType:
   SolderMaskDefined

diff --git a/src/landpatterns/grid-planner.stanza b/src/landpatterns/grid-planner.stanza
@@ -194,6 +194,8 @@ is populated.
     X | O | X  ...
     ...
   ```
+@member Even-Phase
+@member Odd-Phase
 <DOC>
 public defenum StaggerPhase :
   Even-Phase

diff --git a/src/landpatterns/pads.stanza b/src/landpatterns/pads.stanza
@@ -157,6 +157,8 @@ This enum provides flags that can indicate the style of
 pastemask to generate. This can often be useful for
 generating a pastemask layer that conforms to certain
 norms.
+@member NominalPasteMask
+@member NoPasteMask
 <DOC>
 public defenum PasteMaskStyle:
   NominalPasteMask

diff --git a/src/landpatterns/silkscreen.stanza b/src/landpatterns/silkscreen.stanza
@@ -236,6 +236,8 @@ public defmethod build-shape (s:InterstitialOutline, vp:VirtualLP -- side:Side =
 doc: \<DOC>
 Selector for whether the edge lines are
 drawn on the Top / Bottom sides (N/S) or the Left/Right sides (E/W)
+@member NS-Edge
+@member EW-Edge
 <DOC>
 public defenum SilkscreenEdge :
   NS-Edge

diff --git a/src/landpatterns/two-pin/axial.stanza b/src/landpatterns/two-pin/axial.stanza
@@ -82,9 +82,9 @@ Axial Mounting Style
 There are generally two ways to mount an axial component
 on a PCB.
 
-1.  Horizontally - this is the typical method where the
+@member Horz-Mount-Axial Horizontally: this is the typical method where the
   lead axis is parallel with the board surface.
-2.  Vertically - In this configuration, the lead axis is
+@member Vert-Mount-Axial Vertically: In this configuration, the lead axis is
   perpendicular with the board surface, and the lead pointing
   away from the board surface is bent 180 degrees to mate with
   the board surface.

diff --git a/src/protocols/displayport.stanza b/src/protocols/displayport.stanza
@@ -35,8 +35,17 @@ public val DISPLAYPORT_NUM_CONFIGS = 2
 doc: \<DOC>
 @brief DisplayPort Generation enums
 This is a fixed list of possible generation definitions for DisplayPort
+@member DP1p0
+@member DP1p1
+@member DP1p2
+@member DP1p2a
+@member DP1p3
+@member DP1p4
+@member DP1p4a
+@member DP2p0
+@member DP2p1
+@member DP2p1a
 <DOC>
-
 public pcb-enum jsl/protocols/displayport/DPVersion:
   DP1p0  ; 10.80 Gbit/s / 4 lanes =>  2.7 Gbit/s / 10 UI =>  270 MHz clk
   DP1p1  ; 10.80 Gbit/s / 4 lanes =>  2.7 Gbit/s / 10 UI =>  270 MHz clk

diff --git a/src/protocols/ethernet/MII/RGMII.stanza b/src/protocols/ethernet/MII/RGMII.stanza
@@ -52,6 +52,8 @@ In RGMII v2, the spec introduces an optional "Internal Delay"
 feature. Devices that provide this are labeled "RGMII-ID".
 These devices don't require a PCB board delay because the
 delay can be configured in firmware.
+@member RGMII-STD
+@member RGMII-ID
 <DOC>
 public pcb-enum jsl/protocols/ethernet/RGMII/RGMIIVersion:
   RGMII-STD

diff --git a/src/protocols/ethernet/utils.stanza b/src/protocols/ethernet/utils.stanza
@@ -4,6 +4,11 @@ defpackage jsl/protocols/ethernet/utils:
   import jitx
   import jitx/commands
 
+doc: \<DOC>
+@member MII-COL
+@member MII-CS
+@member MII-TXER
+<DOC>
 public pcb-enum jsl/protocols/ethernet/utils/MIIPins :
   MII-COL ; Collision
   MII-CS ; Carrier Sense

diff --git a/src/protocols/memory/lpddr4.stanza b/src/protocols/memory/lpddr4.stanza
@@ -29,6 +29,9 @@ defpackage jsl/protocols/memory/lpddr4 :
 doc: \<DOC>
 @brief LPDDR4 Width enums
 This is a fixed list of possible channel widths for LPDDR4
+@member LPDDR4-x16
+@member LPDDR4-x32
+@member LPDDR4-x64
 <DOC>
 public pcb-enum jsl/protocols/memory/lpddr4/LPDDR4-Width:
   LPDDR4-x16
@@ -50,6 +53,9 @@ public defn num-x16-lanes (width:LPDDR4-Width) -> Int :
 doc: \<DOC>
 @brief LPDDR4 Rank enums
 This is a fixed list of possible ranks for LPDDR4
+@member LPDDR4-Rank1
+@member LPDDR4-Rank2
+@member LPDDR4-Rank3
 <DOC>
 public pcb-enum jsl/protocols/memory/lpddr4/LPDDR4-Rank:
   LPDDR4-Rank1

diff --git a/src/protocols/pcie.stanza b/src/protocols/pcie.stanza
@@ -38,6 +38,13 @@ doc: \<DOC>
 @brief PCI-e Generation enums
 This is a fixed list of possible generation definitions for PCIe
 Can be extended if needed to include PCIE-V3.1, for example
+@member PCIE-V1
+@member PCIE-V2
+@member PCIE-V3
+@member PCIE-V4
+@member PCIE-V5
+@member PCIE-V6
+@member PCIE-V7
 <DOC>
 
 public pcb-enum jsl/protocols/pcie/PCIeVersion:
@@ -52,6 +59,12 @@ public pcb-enum jsl/protocols/pcie/PCIeVersion:
 doc: \<DOC>
 @brief PCI-e Width enums
 This is a fixed list of possible lane widths for PCIe
+@member PCIe-x1
+@member PCIe-x2
+@member PCIe-x4
+@member PCIe-x8
+@member PCIe-x16
+@member PCIe-x32
 <DOC>
 public pcb-enum jsl/protocols/pcie/PCIeWidth:
   PCIe-x1
@@ -69,7 +82,9 @@ public defn PCIe-enum-to-int (en:PCIeWidth) -> Int:
     PCIe-x8  :  8
     PCIe-x16 : 16
     PCIe-x32 : 32
-
+doc: \<DOC>
+@member PCIe-PRSNT#
+<DOC>
 public pcb-enum jsl/bundles/pcie/PCIePins :
   PCIe-PRSNT#
 

diff --git a/src/protocols/sata.stanza b/src/protocols/sata.stanza
@@ -33,6 +33,13 @@ defpackage jsl/protocols/sata:
 doc: \<DOC>
 @brief SATA Generation enums
 This is a fixed list of possible generation definitions for SATA
+@member SATA1p0
+@member SATA2p0
+@member SATA3p0
+@member SATA3p1
+@member SATA3p2
+@member SATA3p3
+@member SATA3p4
 <DOC>
 
 public pcb-enum jsl/protocols/sata/SATAGen:

diff --git a/src/protocols/usb.stanza b/src/protocols/usb.stanza
@@ -163,7 +163,11 @@ public pcb-bundle usb-c-connector :
 ;;;;;;;;;;;;;;;;;;;;;;;;;
 ; Constraints
 ;;;;;;;;;;;;;;;;;;;;;;;;;
-
+doc: \<DOC>
+@member USB2
+@member USB3
+@member USB4
+<DOC>
 public pcb-enum jsl/protocols/usb/USBVersion:
   USB2
   USB3

diff --git a/src/si/TransmissionLine.stanza b/src/si/TransmissionLine.stanza
@@ -13,7 +13,10 @@ defpackage jsl/si/TransmissionLine:
   import core
   import jitx
 
-
+doc: \<DOC>
+@member Single-Ended
+@member Differential
+<DOC>
 public defenum TransmissionStructure:
   Single-Ended
   Differential
@@ -92,4 +95,4 @@ passed `t` object and which will be override with new values.
 @param Z Target characteristic impedance for the structure.
 @param freq Optional frequency to solve for - this includes the dispersion relationships.
 <DOC>
-public defmulti solve-Z (t:TransmissionLine, Z:Double -- freq:Double = ?) -> TransmissionLine
+public defmulti solve-Z (t:TransmissionLine, Z:Double -- freq:Double = ?) -> TransmissionLine
diff --git a/src/symbols/arrows.stanza b/src/symbols/arrows.stanza
@@ -16,6 +16,8 @@ defpackage jsl/symbols/arrows:
 
 doc: \<DOC>
 Select the style of arrow to construct
+@member ClosedArrow
+@member OpenArrow
 <DOC>
 public defenum ArrowStyle :
   ClosedArrow
@@ -113,4 +115,4 @@ public defn construct-arrow (
     shaft-length = shaft-length,
     line-width = line-width
     )
-  construct-arrow(v)
+  construct-arrow(v)
diff --git a/src/symbols/capacitors.stanza b/src/symbols/capacitors.stanza
@@ -60,6 +60,10 @@ public defn set-default-cap-symbol-params (v:CapacitorSymbolParams) -> False :
   DEF_NON_POL_PARAMS = v
 
 
+doc: \<DOC>
+@member Polarized-Straight-Style
+@member Polarized-Curved-Style
+<DOC>
 public defenum PolarizedStyle:
   Polarized-Straight-Style
   Polarized-Curved-Style

diff --git a/src/symbols/decorators.stanza b/src/symbols/decorators.stanza
@@ -34,9 +34,9 @@ public defn ActiveLowDecorator (
   )
 
 doc: \<DOC>
-* `OpenCollectorSink` = Low Side Open Collector Sink. This is the most common version. This
+@member OpenCollectorSink Low Side Open Collector Sink. This is the most common version. This
 is created using a NPN BJT or NMOS FET.
-* `OpenCollectorSource` = High Side Open Collector Source. Less common - this is created using a PNP BJT
+@member OpenCollectorSource High Side Open Collector Source. Less common - this is created using a PNP BJT
 or PMOS FET.
 <DOC>
 public defenum OpenCollectorType:
@@ -146,6 +146,11 @@ public defn ClockDecorator (
   )
 
 
+doc: \<DOC>
+@member InputPin
+@member OutputPin
+@member BidirectionalPin
+<DOC>
 public defenum CardinalityType :
   InputPin
   OutputPin

diff --git a/src/symbols/inductors.stanza b/src/symbols/inductors.stanza
@@ -8,6 +8,11 @@ defpackage jsl/symbols/inductors:
   import jsl/symbols/framework
   import jsl/geometry/basics
 
+doc: \<DOC>
+@member NoBarCore
+@member SingleBarCore
+@member DoubleBarCore
+<DOC>
 public defenum InductorCoreStyle:
   NoBarCore
   SingleBarCore

diff --git a/src/symbols/resistors.stanza b/src/symbols/resistors.stanza
@@ -13,6 +13,10 @@ defpackage jsl/symbols/resistors:
   import jsl/design/Classable
   import jsl/symbols/framework
 
+doc: \<DOC>
+@member TriangleWaveStyle
+@member OpenRectangle
+<DOC>
 public defenum ResistorStyle:
   TriangleWaveStyle
   OpenRectangle

diff --git a/src/symbols/transistors/BJT.stanza b/src/symbols/transistors/BJT.stanza
@@ -9,6 +9,10 @@ defpackage jsl/symbols/transistors/BJT:
   import jsl/geometry/basics
   import jsl/symbols/framework
 
+doc: \<DOC>
+@member NPN
+@member PNP
+<DOC>
 public defenum BJT-Junction :
   NPN
   PNP

diff --git a/src/symbols/transistors/FET.stanza b/src/symbols/transistors/FET.stanza
@@ -10,10 +10,18 @@ defpackage jsl/symbols/transistors/FET:
   import jsl/geometry/basics
   import jsl/symbols/framework
 
+doc: \<DOC>
+@member N-Channel
+@member P-Channel
+<DOC>
 public defenum FET-Junction :
   N-Channel
   P-Channel
 
+doc: \<DOC>
+@member Enhancement
+@member Depletion
+<DOC>
 public defenum FET-Mode :
   Enhancement
   Depletion

diff --git a/src/via-structures.stanza b/src/via-structures.stanza
@@ -221,6 +221,8 @@ Via Signal Identifier Enum
 
 This type distinguishes between single-ended and differential
 via structures.
+@member Via-Single-Ended
+@member Via-Differential
 <DOC>
 public defenum ViaSignalType:
   Via-Single-Ended