Merge pull request #18 from M0stafaRady/RTL_updates4GL

RTL updates
RTimothyEdwards · Aug 28, 2023 · 00f80bf · 00f80bf
2 parents 67006c6 + 5e426be
commit 00f80bf
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Showing 4 changed files with 25 additions and 4 deletions.
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
@@ -187,6 +187,13 @@ assign value_check_plus = (is_offset) ? value_cur_plus : value_cur;
 assign enable_out = enable;
 assign loc_enable = (chain == 1'b1) ? (enable && enable_in) : enable;
 
+// stop_out delayed signal
+reg stop_out_delayed; 
+always @(posedge clkin or negedge resetn)
+	if (resetn == 1'b0)
+		stop_out_delayed <= 0;
+	else:
+		stop_out_delayed <= stop_out;
 // When acting as the high 32 bit word of a 64-bit chained counter:
 //
 // It counts when the low 32-bit counter strobes (strobe == 1).
@@ -210,7 +217,7 @@ always @(posedge clkin or negedge resetn) begin
 	end else if (loc_enable == 1'b1) begin
 	    /* IRQ signals one cycle after stop, if IRQ is enabled	*/
 	    /* IRQ lasts for one cycle only.				*/
-	    irq_out <= (irq_ena) ? (stop_out & ~irq_out) : 1'b0;
+	    irq_out <= (irq_ena) ? (stop_out & ~stop_out_delayed & ~irq_out) : 1'b0;
 
 	    if (updown == 1'b1) begin
 		if (lastenable == 1'b0) begin

diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
@@ -195,6 +195,13 @@ assign enable_out = enable;
 
 assign is_offset = ((updown == 1'b1) && (value_reset == 0));
 
+// stop_out delayed signal
+reg stop_out_delayed; 
+always @(posedge clkin or negedge resetn)
+	if (resetn == 1'b0)
+		stop_out_delayed <= 0;
+	else:
+		stop_out_delayed <= stop_out;
 // When acting as low 32-bit word of a 64-bit chained counter:
 // It sets the output strobe on the stop condition, one cycle early.
 // It stops on the stop condition if "stop_in" is high.
@@ -218,7 +225,7 @@ always @(posedge clkin or negedge resetn) begin
 	end else if (loc_enable == 1'b1) begin
 	    /* IRQ signals one cycle after stop_out, if IRQ is enabled	*/
 	    /* IRQ lasts for one clock cycle only.			*/
-	    irq_out <= (irq_ena) ? (stop_out & ~irq_out) : 1'b0;
+	    irq_out <= (irq_ena) ? (stop_out & ~stop_out_delayed & ~irq_out) : 1'b0;
 
 	    if (updown == 1'b1) begin
 		if (lastenable == 1'b0) begin

diff --git a/verilog/rtl/picosoc.v b/verilog/rtl/picosoc.v
@@ -132,7 +132,7 @@ module picosoc (
     /* PicoRV32 configuration */
     parameter [31:0] STACKADDR = (4*(`MEM_WORDS));       // end of memory
     parameter [31:0] PROGADDR_RESET = 32'h 1000_0000; 
-    parameter [31:0] PROGADDR_IRQ   = 32'h 0000_0000;
+    parameter [31:0] PROGADDR_IRQ   = 32'h 1000_0010;
 
     // Wishbone base addresses
     parameter RAM_BASE_ADR    = 32'h0000_0000;

diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
@@ -181,6 +181,7 @@ module simple_spi_master (
     parameter FINISH = 2'b11; 
 
     reg	  done;
+    reg	  done_delayed;
     reg 	  isdo, hsck, icsb;
     reg [1:0] state;
     reg 	  isck;
@@ -216,7 +217,7 @@ module simple_spi_master (
     assign	  sdoenb = icsb;
     assign	  sdo = isdo;
 
-    assign	  irq_out = irqena & done;
+    assign	  irq_out = irqena & done & ~done_delayed;
     assign	  hk_connect = (enable == 1'b1) ? hkconn : 1'b0;
     assign	  spi_enabled = enable;
 
@@ -226,6 +227,12 @@ module simple_spi_master (
     assign reg_dat_wait = ~done;
     assign reg_dat_do = done ? rreg : ~0;
 
+    always @(posedge clk or negedge resetn) 
+        if (resetn == 1'b0)
+            done_delayed <= 0; 
+        else 
+            done_delayed <= done;
+
     // Write configuration register
     always @(posedge clk or negedge resetn) begin
         if (resetn == 1'b0) begin