Fixed two syntax errors per PR #20 from Mostafa Rady (except that

the pull request contains too many other changes, so I'm just doing this one by hand).
RTimothyEdwards · Aug 28, 2023 · 650c066 · 650c066
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diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
@@ -192,7 +192,7 @@ reg stop_out_delayed;
 always @(posedge clkin or negedge resetn)
 	if (resetn == 1'b0)
 		stop_out_delayed <= 0;
-	else:
+	else
 		stop_out_delayed <= stop_out;
 // When acting as the high 32 bit word of a 64-bit chained counter:
 //

diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
@@ -200,7 +200,7 @@ reg stop_out_delayed;
 always @(posedge clkin or negedge resetn)
 	if (resetn == 1'b0)
 		stop_out_delayed <= 0;
-	else:
+	else
 		stop_out_delayed <= stop_out;
 // When acting as low 32-bit word of a 64-bit chained counter:
 // It sets the output strobe on the stop condition, one cycle early.