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Staging/adf5611 dev #2411
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Staging/adf5611 dev #2411
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some small initial comments on my side.
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@amiclaus All initial changes have been made. Thanks. |
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these are the changes that i could think of, maybe there are a few more needed but the compiler will guide you
you should perform a rebase on main
branch once #2412 is merged, hopefully today
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@buha All changes have been made to date. Thanks. |
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looks good but you need to rebase it on main
"Signed-off-by: Jude Osemene <jude.osemene@analog.com>"
"Signed-off-by: Jude Osemene <jude.osemene@analog.com>"
"Signed-off-by: Jude Osemene <jude.osemene@analog.com>"
Add initial project files for both basic and IIO examples for ADF5611 "Signed-off-by: Jude Osemene <jude.osemene@analog.com>"
Add README.rst documentation file for project alongside other documentation related files. "Signed-off-by: Jude Osemene <jude.osemene@analog.com>"
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Done, thanks |
The ADF5611and ADF5612 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference source. The wideband microwave voltage controlled oscillator (VCO) design permits frequency operation from 7300 MHz to 14600 MHz for ADF5611 and from 7300 MHz to 8500 MHz for ADF5612 at a single radio frequency (RF) output. A series of frequency dividers with a differential frequency output allows operation from 57 MHz to 14600MHz for ADF5611, while ADF5612 is limited to 57MHz to 8500MHz. Analog and digital power supplies for the PLL circuitry range from 3.15 V to 3.45 V, and the VCO supplies are between 4.75 V and 5.25 V. Both ADF5611 and ADF5612 has an integrated VCO with a fundamental frequency of 3650 MHz to 7300 MHz. These frequencies are internally doubled and routed to the RFOUT pin. An additional differential output allows the doubled VCO frequency to be divided by 1, 2, 4, 8, 16, 32, 64, or 128, allowing the user to generate RF output frequencies as low as 57 MHz. A simple 3 or 4 wire serial port interface (SPI) provides control of all on-chip registers. To conserve power, this divider block can be disabled when not needed through the SPI interface. Likewise, the output power for both the single- ended output and the differential output are programmable. Their integrated phase detector (PD) and delta-sigma (Δ-Σ) modulator, capable of operating at up to 100 MHz, permit wide loop bandwidths and fast frequency tuning with a typical spurious level of −100 dBc. With phase noise levels from −115 dBc/Hz at 7.3 GHz to −109 dBc/Hz at 14.6 GHz and −112 dBc/Hz at 8.5 GHz RFOUT respectively, both synthesizers are equipped to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. The low phase noise floor eliminates any contribution to modulator and mixer noise floor in transmitter applications.
Pull Request Description
This new driver is developed for control of ADF5611 and ADF5612 frequency generation products which will be released in January of 2025, and also has built-in IIO support. The features developed are categorized as follows:
PR Type
PR Checklist