FAQ
The ReSDMAC is based on what I believe are the schematics for the SDMAC Rev 3 with my interpretation of the fixes implemented in SDMAC Rev 4, therefore it will not implement the features of the SDMAC Rev 2, this includes the XT/AT interface, the WTC and DAW registers and also the terminal count features.
ReSDMAC can work with either revision of Ramsey, For Ramsey Rev 7 there are no special instructions it is simply PnP. To function correctly with a Rev 4 Ramsey, it is recomended to set the transfer mask in HDToolBox to 0x7ffffffc for each partition.
The ReSDMAC aims to improve compatibility with accelerators by providing more consistent signal timing though the use of a PLL for generating the phase shifted clk signals. Timing often appears to be an issue with the original SDMAC chips.
Note
The following is all speculation; however, it is based on my observations of the SDMAC internal circuitry.
Inside the SDMAC phase-shifted versions of the 25Mhz system clock are produced by chaining together up to six inverters as shown below.
The phase shift in degrees can be calculated using the following formula:
-
$p = 40ns$ = Time period of clk signal @ 25Mhz. -
$td = n \times pd$ = Signal delay time. -
$n = 6$ = Number of inverters in the chain. -
$pd = 3ns ± 1ns$ = Typical propagation delay for similar 2 micron cmos gate arrays of the era
These propagation delays would likely vary within the tolerance from chip to chip depending on various variables such as location on the wafer during manufacturing, temperature and voltage when operating.
- if we assume that pd = 2ns, then phase shift = 108 degrees.
- if we assume that pd = 3ns, then phase shift = 162 degrees.
- if we assume that pd = 4ns, then phase shift = 216 degrees.
it's clear to see the tolerance in the propagation delay can give rise to significant differences in the phase shift for these clk signals. This I believe is likely the cause of the SDMAC lottery with timing.
Also note other custom chips in the A3000 such as Ramsey, Gary and Buster take a CLK90 signal as an input for their phase-shifted clocks.
For further reading on what variables could affect timing, there is an interesting article here with lots of detail Propagation Delay in CMOS Inverters
To answer this first you need to understand that the DMA controller is technically split across the two chips (SDMAC & Ramsey). The spit across the IC's is necessitated by the fact that the DMA controller operates with a 32 bit data and address bus. There are simply not enough pins on the PLCC 84 package to accommodate 64 pins required for buses and the pins for the other control signals.
As Ramsey already had the 32 address pins it was logical to make these bidirectional on Ramsey so they can be used to drive the address bus when the SDMAC is the bus master and performing DMA transfers
Ramsey contains an ACR (Address Count Register) which is loaded with the start address of the DMA transfer. When the _DMAEN signal from SDMAC is asserted Ramsey drives the address from the ACR on to the address bus. After each DMA transfer cycle completes, Ramsey will automatically increment the ACR by the correct amount, it achieves this by monitoring the cycle termination signals.
Now comes the important part :P
-
Rev 4 Ramsey: The
ACRcan only be preset to an even longword boundary (bits 1 and 0 are always written as 0,0) -
Rev 7 Ramsey: The
ACRcan only be preset to an even word boundary (bit 0 is always written as 0).
The consequences of this are that a Rev 4 ramsey can only address memory locations ending in 0x0, 0x4, 0x8 or 0xC.
But a Rev 7 Ramsey and address memory locations ending in 0x0, 0x2, 0x4, 0x6, 0x8, 0xA, 0xC and 0xE
Why does this matter? Well, as far as we can tell the scsi.device will detect if you are using a Rev 2 or 4 SDMAC, if a Rev 4 SDMAC is detected the scsi.device will assume you have a Rev 7 Ramsey installed.
In this scenario the operating system may try to perform DMA transfers to the additional address alignments that the Rev 7 Ramsey is capable of however the system may well be fitted with a Rev 4 Ramsey as there is no check to see which revision of Ramsey is present.
what does this mean for compatibility
| Compatibility | Ramsey 4 | Ramsey 7 |
|---|---|---|
| SDMAC 2 | ✅ | ✅ |
| SDMAC 4 | ❌ except when setting the transfer mask | ✅ |
| ReSDMAC | ❌ except when setting the transfer mask | ✅ |
So why do I need to set the transfer mask?
Setting the mask tells the scsi.device to restrict DMA transfers to longword aligned transfers that both revisions of Ramsey can support.